公开(公告)号：US08754477B2

公开(公告)日：2014-06-17

申请号：US13277872

申请日：2011-10-20

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/324 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78654

摘要： A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.

摘要翻译： 公开了一种制造方法和具有多个位错结构的半导体器件。 示例性半导体器件包括覆盖半导体衬底的顶表面的栅极结构和设置在栅极结构的侧壁上且覆盖衬底顶表面的第一栅极间隔。 半导体器件还包括结晶半导体材料，其覆盖半导体衬底的顶表面并与第一栅极间隔物的侧壁相邻。 半导体器件还包括设置在第一栅极间隔物的侧壁上并覆盖结晶的半导体材料的第二栅极间隔物。 半导体器件还包括设置在半导体衬底中的第一应力区域和设置在半导体衬底和晶体化半导体材料中的第二应力区域。

公开(公告)号：US20130187221A1

公开(公告)日：2013-07-25

申请号：US13356207

申请日：2012-01-23

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7849 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7613 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

摘要翻译： 形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。 该方法还包括在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。

公开(公告)号：US20130099314A1

公开(公告)日：2013-04-25

申请号：US13277872

申请日：2011-10-20

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/324 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78654

摘要： A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.

摘要翻译： 公开了一种制造方法和具有多个位错结构的半导体器件。 示例性半导体器件包括覆盖半导体衬底的顶表面的栅极结构和设置在栅极结构的侧壁上且覆盖衬底顶表面的第一栅极间隔。 半导体器件还包括结晶半导体材料，其覆盖半导体衬底的顶表面并与第一栅极间隔物的侧壁相邻。 半导体器件还包括设置在第一栅极间隔物的侧壁上并覆盖结晶的半导体材料的第二栅极间隔物。 半导体器件还包括设置在半导体衬底中的第一应力区域和设置在半导体衬底和晶体化半导体材料中的第二应力区域。

公开(公告)号：US08828817B2

公开(公告)日：2014-09-09

申请号：US13356207

申请日：2012-01-23

申请人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

发明人： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC分类号： H01L21/8238

CPC分类号： H01L29/7849 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7613 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

摘要翻译： 形成半导体器件的方法包括在衬底上执行第一预非晶体注入工艺，其中衬底具有栅叠层。 该方法还包括在衬底上形成第一应力膜。 该方法还包括对基板和第一应力膜执行第一退火处理。 该方法还包括在退火的衬底上执行第二预非晶体注入工艺，在衬底上形成第二应力膜，并对衬底和第二应力膜执行第二退火处理。