公开(公告)号：US20240321893A1

公开(公告)日：2024-09-26

申请号：US18612438

申请日：2024-03-21

Applicant: COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Heimanu NIEBOJEWSKI ,  Benoit BERTRAND ,  Thomas BEDECARRATS

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/66977 ,  H01L29/7613

Abstract: One aspect of the invention relates to an electronic circuit (1) comprising:



a semiconductor layer (2), referred to as “qubit layer”;
a separation layer (42) extending in contact with the qubit layer (2);
first conductive electrodes (61), referred to as “coupling rows”, extending in parallel to the qubit layer (2);
second conductive electrodes (62), referred to as “coupling columns”, extending in parallel to the qubit layer (2);
third conductive electrodes (71), referred to as “control rows”, extending over the spacer (42); and
conductive vias (72), referred to as “control vias”, extending perpendicularly to the face of the qubit layer (2) from the spacer (42) and having one end disposed in proximity to the qubit layer (2).

公开(公告)号：US11749721B2

公开(公告)日：2023-09-05

申请号：US16146899

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/00 ,  H01L29/15 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  G06N10/00 ,  H01L29/82 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/778 ,  H01L29/165 ,  H01L29/12

CPC classification number: H01L29/157 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/02362 ,  H01L29/401 ,  H01L29/42312 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7831 ,  H01L29/82 ,  H01L29/127 ,  H01L29/165 ,  H01L29/7782 ,  H01L29/7786

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.

公开(公告)号：US20190198614A1

公开(公告)日：2019-06-27

申请号：US15852050

申请日：2017-12-22

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  International Business Machines Corporation

Inventor： Shay REBOH ,  Kangguo CHENG ,  Remi COQUAND ,  Nicolas LOUBET

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L29/423 ,  H01L21/225 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/10 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7613 ,  H01L29/775

Abstract: A method of fabrication of a semiconductor device including the implementation of the following steps: fabrication of a stack including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, such that the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure intended to be made; and thermal treatment of the stack at a temperature which causes surface migration of atoms of the second semiconductor of the second portion towards at least one part of the first portion which exhibits at least one free surface and at which the nanostructure containing at least atoms of the second semiconductor is formed.

公开(公告)号：US10079286B2

公开(公告)日：2018-09-18

申请号：US15472438

申请日：2017-03-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Greg Charles Baldwin

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L21/266 ,  H01L29/66 ,  H01L29/45 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L29/41758 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/092 ,  H01L27/15 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/122 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7391 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/7836

Abstract: Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.

公开(公告)号：US10038084B2

公开(公告)日：2018-07-31

申请号：US15616289

申请日：2017-06-07

Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

Inventor： Seong Jin Koh ,  Pradeep Bhadrachalam ,  Liang-Chieh Ma

IPC: H01L29/66 ,  H01L29/41 ,  H01L29/24 ,  H01L29/06 ,  H01L29/12 ,  B82Y40/00 ,  B82Y10/00 ,  H01L29/08 ,  H01L29/76 ,  H01L29/88

CPC classification number: H01L29/66977 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0895 ,  H01L29/122 ,  H01L29/127 ,  H01L29/24 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L29/7827 ,  H01L29/882 ,  Y10S977/774 ,  Y10S977/937

Abstract: Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

公开(公告)号：US09997597B2

公开(公告)日：2018-06-12

申请号：US15671632

申请日：2017-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/74 ,  H01L31/0328 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02664 ,  H01L29/127 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L29/7827

Abstract: A method for forming a vertical single electron transistor includes forming a heterostructured nanowire having a SiGe region centrally disposed between an upper portion and a lower portion in the nanowire. An oxide is deposited to cover the SiGe region, and a condensation process is performed to convert the SiGe to oxide and condense Ge to form an island between the upper portion and the lower portion of the nanowire. A bottom contact is formed about the lower portion, a first dielectric layer is formed on the bottom contact and a gate structure is formed about the island on the first dielectric layer. A second dielectric layer is formed on the gate structure, and a top contact is formed on the second dielectric layer.

公开(公告)号：US20170372826A1

公开(公告)日：2017-12-28

申请号：US15195248

申请日：2016-06-28

Applicant: Alcatel-Lucent USA Inc.

Inventor： Gavin D. Scott

IPC: H01F7/06

CPC classification number: G11C11/14 ,  B82Y10/00 ,  B82Y25/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  H01F10/3254 ,  H01L29/0665 ,  H01L29/66984 ,  H01L29/7613 ,  H01L43/12

Abstract: We disclose a magnetic device having a pair of coplanar thin-film magnetic electrodes arranged on a substrate with a relatively small edge-to-edge separation. In an example embodiment, the magnetic electrodes have a substantially identical footprint that can be approximated by an ellipse, with the short axes of the ellipses being collinear and the edge-to-edge separation between the ellipses being smaller than the size of the short axis. In some embodiments, the magnetic electrodes may have relatively small tapers that extend toward each other from the ellipse edges in the constriction area between the electrodes. Some embodiments may also include an active element inserted into the gap between the tapers and electrical leads connected to the magnetic electrodes for passing electrical current through the active element. When subjected to an appropriate external magnetic field, the magnetic electrodes can advantageously be magnetized to controllably enter parallel and antiparallel magnetization states.

公开(公告)号：US09825161B2

公开(公告)日：2017-11-21

申请号：US14773581

申请日：2014-03-09

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Yutaka Majima ,  Toshiharu Teranishi ,  Kazuhiko Matsumoto ,  Kenzo Maehashi ,  Tomofumi Susaki ,  Yasuhide Ohno ,  Kosuke Matsuzaki ,  Guillaume Hubert Frederic Hackenberger

IPC: H01L29/76 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7613 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0665 ,  H01L29/127 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/66439

Abstract: Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.

公开(公告)号：US09506892B2

公开(公告)日：2016-11-29

申请号：US14302842

申请日：2014-06-12

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Kazuhiko Matsumoto ,  Atsuhiko Kojima ,  Satoru Nagao ,  Masanori Katou ,  Yutaka Yamada ,  Kazuhiro Nagaike ,  Yasuo Ifuku ,  Hiroshi Mitani

IPC: G01N27/414 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/76

CPC classification number: G01N27/4145 ,  B82Y10/00 ,  B82Y30/00 ,  G01N27/4146 ,  H01L29/068 ,  H01L29/42364 ,  H01L29/7613

Abstract: A sensor capable of detecting detection targets that are necessary to be detected with high sensitivity is provided.It comprises a field-effect transistor 1A having a substrate 2, a source electrode 4 and a drain electrode 5 provided on said substrate 2, and a channel 6 forming a current path between said source electrode 4 and said drain electrode 5; wherein said field-effect transistor 1A comprises: an interaction-sensing gate 9 for immobilizing thereon a specific substance 10 that is capable of selectively interacting with the detection targets; and a gate 7 applied a voltage thereto so as to detect the interaction by the change of the characteristic of said field-effect transistor 1A.

公开(公告)号：US09362919B1

公开(公告)日：2016-06-07

申请号：US14579763

申请日：2014-12-22

Applicant: University of Notre Dame du Lac

Inventor： Behnam Sedighi ,  Michael Niemier ,  X. Sharon Hu ,  Joseph J. Nahas

IPC: H03K19/195 ,  H01L29/06 ,  H01L29/16 ,  H01L29/778 ,  H01L29/08

CPC classification number: H03K19/195 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/127 ,  H01L29/1606 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/778

Abstract: A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits. Negative differential resistance (NDR) behavior of SymFETs leads to hysteresis in inverters and buffers, and can be used to build simple Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in circuits similar to all-n-type or dynamic logic. For example, latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY gates may employ SymFETs. Such SymFET-based devices require fewer transistors than static CMOS-based designs.

Abstract translation: 布尔门包括用于低功率信息处理的至少一个对称隧道场效应晶体管（SymFET）。 SymFET是需要低功耗和中等速度要求的应用的理想选择，并且比CMOS电路表现出更好的动态能量效率。 SymFET的负差分电阻（NDR）行为导致逆变器和缓冲器中的滞后，并可用于构建简单的施密特触发器。 此外，伪SymFET负载可以用于类似于全n型或动态逻辑的电路中。 例如，锁存器和触发器以及NAND，NOR，IMPLY和MAJORITY门可以采用SymFET。 与基于静态CMOS的设计相比，这种基于SymFET的器件需要更少的晶体管。