公开(公告)号：US06323768B2

公开(公告)日：2001-11-27

申请号：US09756808

申请日：2001-01-09

申请人： Simon Bessendorf ,  Richard V. Kemper ,  William A. Sciarretta ,  Edward T. Lewis

发明人： Simon Bessendorf ,  Richard V. Kemper ,  William A. Sciarretta ,  Edward T. Lewis

IPC分类号： G08B1318

CPC分类号： H01L31/1125

摘要： The invention provides apparatus and methods for detecting electromagnetic energy using an array of detectors arranged in at least one row and multiple columns. A single crystal body has multiple doped regions disposed therein. Each one of the detectors produces charge in a corresponding one of the doped regions in the body in response to electromagnetic energy impinging upon that detector. A first charge transfer device includes an output port and multiple serially coupled charge storage cells including multiple first charge transfer regions disposed in the body parallel to the row, or rows, of detectors. Multiple second charge transfer devices include multiple second charge transfer regions disposed in the body transverse to the row, or rows, of detectors and the charge storage cells. Each one of the second charge transfer regions is adapted to transfer charge produced in a corresponding one of the doped regions to a corresponding one of the charge storage cells. Each one of the doped regions corresponding to one of the detectors has a doping profile adapted to produce an electric field in a direction from the doped region toward a corresponding one of the multiple second charge transfer regions. Such an arrangement allows dual polarization detection with little or no modification of the system configuration.

公开(公告)号：US4797579A

公开(公告)日：1989-01-10

申请号：US78142

申请日：1987-07-27

申请人： Edward T. Lewis

发明人： Edward T. Lewis

IPC分类号： H03K19/0185 ,  H03K4/94 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0175

CPC分类号： H03K4/94 ,  H03K17/6872

摘要： A CMOS output driver having precise control of rise and fall times of signals generated from the output driver on a VLSI semiconductor chip. Two time-dependent voltage generators provide a separate ramp signal to each one of the gates of a CMOS inverter circuit. The ramp signal characteristics of each voltage generator are determined by the combination of a controlled current source charging a known capacitance.

摘要翻译： CMOS输出驱动器具有精确控制从VLSI半导体芯片上的输出驱动器产生的信号的上升和下降时间。 两个时间依赖的电压发生器为CMOS反相器电路的每个栅极提供单独的斜坡信号。 每个电压发生器的斜坡信号特性由对已知电容充电的受控电流源的组合确定。

公开(公告)号：US4675838A

公开(公告)日：1987-06-23

申请号：US667199

申请日：1984-11-01

申请人： Moshe Mazin ,  Edward T. Lewis

发明人： Moshe Mazin ,  Edward T. Lewis

IPC分类号： G06F7/50 ,  G06F7/507 ,  G06F7/508 ,  G06F17/10

CPC分类号： G06F7/507

摘要： A multibit digital adder is shown wherein a pair of carry generating circuitries is disposed between single adders for each bit in the digital numbers to be added, each one of such carry generating circuitries being responsive to a different carry-in signal and to the level of the bits applied to the associated single bit adder to produce the proper carry-in signal to the following single bit adder.

摘要翻译： 示出了一种多位数字加法器，其中在要添加的数字数字中的每个位的单个加法器之间设置一对进位产生电路，这些进位生成电路中的每一个响应于不同的进位输入信号和 这些位应用于相关联的单位加法器，以产生适当的进位信号给以后的单位加法器。

公开(公告)号：US5002897A

公开(公告)日：1991-03-26

申请号：US406644

申请日：1989-09-13

申请人： Edward T. Lewis ,  Dale L. Montrone

发明人： Edward T. Lewis ,  Dale L. Montrone

IPC分类号： H01L27/095

CPC分类号： H01L27/095

摘要： A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.

摘要翻译： 称为互补金属电极半导体（CMES）的半导体器件具有在衬底上互连的p型和n型硅MESFET，其中p型MESFET的p沟道中注入n型势垒增强。 提供了制造结构和方法，用于形成具有非常低功率，低电压，低噪声和高速特性的CMES逻辑逆变器。

公开(公告)号：US4704701A

公开(公告)日：1987-11-03

申请号：US667198

申请日：1984-11-01

申请人： Moshe Mazin ,  Edward T. Lewis

发明人： Moshe Mazin ,  Edward T. Lewis

IPC分类号： G06F7/50 ,  G06F7/507 ,  G06F7/508

CPC分类号： G06F7/507 ,  G06F2207/3876

摘要： A multibit digital adder wherein a proper carry-out signal is generated simultaneously in different parts of such adder.

摘要翻译： 一种多位数字加法器，其中在这种加法器的不同部分中同时产生适当的进位信号。

公开(公告)号：US06239702B1

公开(公告)日：2001-05-29

申请号：US09038251

申请日：1998-03-10

申请人： Simon Bessendorf ,  Richard V. Kemper ,  William A. Sciarretta ,  Edward T. Lewis

发明人： Simon Bessendorf ,  Richard V. Kemper ,  William A. Sciarretta ,  Edward T. Lewis

IPC分类号： G08B1318

CPC分类号： H01L31/1125

摘要： The invention provides apparatus and methods for detecting electromagnetic energy using an array of detectors arranged in at least one row and multiple columns. A single crystal body has multiple doped regions disposed therein. Each one of the detectors produces charge in a corresponding one of the doped regions in the body in response to electromagnetic energy impinging upon that detector. A first charge transfer device includes an output port and multiple serially coupled charge storage cells including multiple first charge transfer regions disposed in the body parallel to the row, or rows, of detectors. Multiple second charge transfer devices include multiple second charge transfer regions disposed in the body transverse to the row, or rows, of detectors and the charge storage cells. Each one of the second charge transfer regions is adapted to transfer charge produced in a corresponding one of the doped regions to a corresponding one of the charge storage cells. Each one of the doped regions corresponding to one of the detectors has a doping profile adapted to produce an electric field in a direction from the doped region toward a corresponding one of the multiple second charge transfer regions. Such an arrangement allows dual polarization detection with little or no modification of the system configuration.

公开(公告)号：US5793194A

公开(公告)日：1998-08-11

申请号：US744260

申请日：1996-11-06

申请人： Edward T. Lewis

发明人： Edward T. Lewis

IPC分类号： G05F3/20 ,  G05F3/24 ,  H03F1/30 ,  G05F3/04

CPC分类号： H03F1/301 ,  G05F3/205 ,  G05F3/247

摘要： Bias networks for producing a predetermined bias current for another circuit are provided. The bias networks include compensation subcircuits which provide compensation for process variations in the transistors in the network. Circuit implementations which allow for compensation for power supply voltage variations are also provided. The bias networks include a biasing transistor and a corresponding compensation transistor on the same chip which compensation transistor will have substantially the same process variations as the biasing transistor. The compensation transistor is interposed at a node in a control path and draws current at the node such that a change in the current drawn by the compensation transistor causes a change in the input voltage of the biasing transistor to thereby adjust the bias current produced by the transistor to maintain the bias current within design specifications despite process variations. Bias circuit configurations for a cascode amplifier, a differential amplifier, and a current mirror are provided.

摘要翻译： 提供了用于产生用于另一电路的预定偏置电流的偏置网络。 偏置网络包括为网络中的晶体管中的工艺变化提供补偿的补偿子电路。 还提供允许补偿电源电压变化的电路实现。 偏置网络包括在同一芯片上的偏置晶体管和相应的补偿晶体管，补偿晶体管将具有与偏置晶体管基本相同的工艺变化。 补偿晶体管插入在控制路径中的节点处并且在节点处吸取电流，使得由补偿晶体管汲取的电流的变化导致偏置晶体管的输入电压的变化，从而调节由偏置晶体管产生的偏置电流 晶体管，尽管工艺变化，仍然保持设计规格内的偏置电流。 提供了共源共栅放大器，差分放大器和电流镜的偏置电路配置。

公开(公告)号：US5561429A

公开(公告)日：1996-10-01

申请号：US852877

申请日：1986-04-16

申请人： M. Halberstam ,  James E. Meister ,  Moshe Mazin ,  Dennis A. Henlin ,  Jun-ichi Sano ,  Edward T. Lewis

发明人： M. Halberstam ,  James E. Meister ,  Moshe Mazin ,  Dennis A. Henlin ,  Jun-ichi Sano ,  Edward T. Lewis

IPC分类号： G06F17/30 ,  G11C15/00 ,  G06F7/02

CPC分类号： G06F17/30982 ,  G11C15/00

摘要： A content limit addressable memory (CLAM) having a plurality of lower and upper limits stored therein for comparison to corresponding subfields of an input word. Each corresponding upper and lower limit forms a bracket. Corresponding brackets form a window. The brackets correspond to the subfields and are of the same number of bits. The brackets and subfields are alterable in width to allow each bracket and subfield to have any number of bits in multiples of two. A valid match of the input word with any window can occur with any combination of the brackets of a window matching or not matching the corresponding subfields of the input word. A plurality of outputs corresponding to each of the windows indicates a match of the corresponding window to the input word. Additionally, the CLAM can compare data stored therein against an applied window with the matching operations as described above.

摘要翻译： 存储有多个下限和上限的内容限制可寻址存储器（CLAM），用于与输入字的相应子字段进行比较。 每个对应的上限和下限形成一个支架。 相应的括号形成一个窗口。 括号对应于子字段并且具有相同的位数。 括号和子字段的宽度是可变的，以允许每个括号和子字段具有任意数量的二进制数。 输入字与任何窗口的有效匹配可以与匹配或不匹配输入字的相应子字段的窗口的括号的任意组合发生。 对应于每个窗口的多个输出表示对应的窗口与输入单词的匹配。 此外，CLAM可以将如上所述的匹配操作来比较存储在其中的数据与应用的窗口。

公开(公告)号：US5361264A

公开(公告)日：1994-11-01

申请号：US20900

申请日：1993-02-22

申请人： Edward T. Lewis

发明人： Edward T. Lewis

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318385 ,  G01R31/318555

摘要： Mode programmable VLSI CMOS data registers perform on-chip self-test. A first data register performs storage or transfer of data, operates in a scan mode or generates pseudo-random numbers (PRN). A second data register performs storage or transfer of data, operates in a scan mode or performs signature analysis. Data initialization of the registers occurs automatically when operating in a test mode.

摘要翻译： 模式可编程VLSI CMOS数据寄存器执行片上自检。 第一数据寄存器执行数据的存储或传输，以扫描模式运行或产生伪随机数（PRN）。 第二数据寄存器执行数据的存储或传输，以扫描模式运行或执行签名分析。 在测试模式下运行时，寄存器的数据初始化会自动发生。

公开(公告)号：US4710649A

公开(公告)日：1987-12-01

申请号：US850642

申请日：1986-04-11

申请人： Edward T. Lewis

发明人： Edward T. Lewis

IPC分类号： H03K19/0948 ,  H03K19/094

CPC分类号： H03K19/0948

摘要： Unified CMOS logic circuits are based on a structured implementation of transmission-gates. The basic logic building blocks for AND and OR circuits comprise a plurality of transmission-gates some of which may be simplified to a reduced form of a single pass transistor resulting in fewer transistors for implementing logic functions without loss of logic circuit performance characteristics. Three variable logic functions and higher order logic functions are easily implemented. Generally, the required VLSI chip area is minimized as a result of this structured transmission-gate approach.

摘要翻译： 统一的CMOS逻辑电路基于传输门的结构化实现。 AND和OR电路的基本逻辑构建块包括多个传输门，其中一些传输门可以简化为简单形式的单通道晶体管，导致用于实现逻辑功能的更少的晶体管，而不损失逻辑电路性能特性。 三个可变逻辑功能和更高阶的逻辑功能很容易实现。 通常，由于这种结构化的传输门方法，所需的VLSI芯片面积被最小化。