公开(公告)号：US4675838A

公开(公告)日：1987-06-23

申请号：US667199

申请日：1984-11-01

申请人： Moshe Mazin ,  Edward T. Lewis

发明人： Moshe Mazin ,  Edward T. Lewis

IPC分类号： G06F7/50 ,  G06F7/507 ,  G06F7/508 ,  G06F17/10

CPC分类号： G06F7/507

摘要： A multibit digital adder is shown wherein a pair of carry generating circuitries is disposed between single adders for each bit in the digital numbers to be added, each one of such carry generating circuitries being responsive to a different carry-in signal and to the level of the bits applied to the associated single bit adder to produce the proper carry-in signal to the following single bit adder.

摘要翻译： 示出了一种多位数字加法器，其中在要添加的数字数字中的每个位的单个加法器之间设置一对进位产生电路，这些进位生成电路中的每一个响应于不同的进位输入信号和 这些位应用于相关联的单位加法器，以产生适当的进位信号给以后的单位加法器。

公开(公告)号：US4599704A

公开(公告)日：1986-07-08

申请号：US567842

申请日：1984-01-03

申请人： Moshe Mazin

发明人： Moshe Mazin

IPC分类号： G11C17/12 ,  G11C17/00

CPC分类号： G11C17/12

摘要： A non-volatile integrated circuit memory is provided having an array of memory elements selectively programmable to store complimentary binary data, each one of such memory elements being formed in a different region of the integrated circuit and having an address terminal, an output terminal, a ground terminal, and a power supply terminal. Those memory cells programmed into a first logical state are provided with transistor action between the output terminal and the power supply terminal and are inhibited from having transistor action between the output terminal and the ground terminal. Conversely, those memory cells programmed to store the complementary logic state are inhibited from having transistor action between the output terminal and the power supply terminal and are provided with transistor action between the ground terminal and the output terminal. In either programmed state, the transistor action is controlled by signals fed to the address terminal of the cells. With such arrangement, since transistor action is prevented between the power supply terminal and the ground terminal of each cell, an electrical open-circuit is always present to the power supply with the result that a precharge cycle is not required during memory addressing to reduce power. The elimination of such pre-charge cycle thereby eliminates the time delays inherent with the precharge cycle circuitry to thereby increase the operating speed of the memory and, further, the elimination of the circuitry increases the storage capacity of the ROM by making more chip area available for memory cells.

摘要翻译： 提供了一种非易失性集成电路存储器，其具有可选地可编程以存储互补二进制数据的存储器元件阵列，这些存储器元件中的每一个形成在集成电路的不同区域中，并且具有地址端子，输出端子， 接地端子和电源端子。 被编程为第一逻辑状态的那些存储器单元在输出端子和电源端子之间提供晶体管作用，并且被禁止在输出端子和接地端子之间具有晶体管作用。 相反，被编程为存储互补逻辑状态的存储单元被禁止在输出端子和电源端子之间具有晶体管作用，并且在接地端子和输出端子之间提供晶体管作用。 在编程状态下，晶体管的动作由馈送到单元的地址端子的信号控制。 通过这种布置，由于在每个单元的电源端子和接地端子之间防止了晶体管的动作，电源总是存在电开路，结果是在存储器寻址期间不需要预充电循环以减少功率 。 消除这种预充电循环从而消除了预充电循环电路固有的时间延迟，从而提高存储器的工作速度，此外，电路的消除通过使更多的芯片面积可用来增加ROM的存储容量 用于记忆细胞。

公开(公告)号：US4901285A

公开(公告)日：1990-02-13

申请号：US316590

申请日：1989-02-27

申请人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

发明人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

IPC分类号： G11C17/12

CPC分类号： G11C17/126

摘要： An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.

摘要翻译： 一种具有多条行线的集成电路存储器; 多条选择线; 多个输出线; 多个存储单元; 每对存储器单元具有耦合到所述多条输出线中的选择一条输出线的公共输出和耦合到所述多条行线中的选择一条线的公共地址输入，其中所选择的所述一对存储器单元中的存储单元的模糊性 耦合到所述多行输入行中的选择一行和所述多条输出行中的选择一行由所耦合的所述多条选择行中的两个选定行选择。 还提供了响应于输入地址以启用多条行线中的选择行的第一解码器，以及响应于行线和输入地址的第二解码器，用于启用选择线中的选择线 其对应于具有启用行行的存储器单元对。

公开(公告)号：US4506349A

公开(公告)日：1985-03-19

申请号：US451689

申请日：1982-12-20

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： G11C11/411 ,  G11C11/412 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  G11C11/40

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/108 ,  Y10S257/903

摘要： A memory cell of the general type employing one pair of IGFETs defining data nodes and cross-coupled in a latch circuit configuration for storing data, and another pair of IGFETs serving as transmission gates to selectively couple data into or out of the cell. A circuit technique provides fast writing speed by avoiding the use of load resistors in either the charge or discharge paths for the data nodes and yet ensures that the data nodes are pulled either fully to logic high or fully to logic low, as the case may be, without limitation by threshold voltage offset between the gate and source terminals of the IGFETs serving as transmission gates. High impedance leakage current discharge resistances are included, and serve only the function of discharging leakage at the nodes to maintain memory. In the disposed circuit configurations, the latch IGFETs are of opposite channel conductivity type compared to the gating IGFETs. Various alternative forms of suitable high impedance leakage current resistances are disclosed, including a resistive sea above the cell and leakage paths included within the gating IGFETs. The high impedance leakage current discharge resistances may be eliminated to provide a dynamic memory cell.

摘要翻译： 一般类型的存储单元采用定义数据节点的一对IGFET和用于存储数据的锁存电路配置的交叉耦合，以及用作传输门的另一对IGFET，用于选择性地将数据耦合到单元或从单元中耦合。 电路技术通过避免在数据节点的充电或放电路径中使用负载电阻器来提供快速的写入速度，并且确保将数据节点完全拉至逻辑高电平或完全拉至逻辑低电平（视情况而定） 而不限于用作传输门的IGFET的栅极和源极端子之间的阈值电压偏移。 包括高阻抗泄漏电流放电电阻，并且仅用于在节点处泄漏泄漏以维持存储器的功能。 在布置的电路配置中，与门控IGFET相比，锁存器IGFET具有相反的沟道导电类型。 公开了适当的高阻抗泄漏电流电阻的各种替代形式，包括在电池单元之上的电阻海和包括在门控IGFET内的泄漏路径。 可以消除高阻抗漏电放电电阻以提供动态存储单元。

公开(公告)号：US4484087A

公开(公告)日：1984-11-20

申请号：US478015

申请日：1983-03-23

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： H03K3/354 ,  H01L27/11 ,  H03K3/356 ,  H03K3/3562 ,  G11C19/28 ,  H03K19/096 ,  H03K23/22

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H03K3/356104 ,  H03K3/35625

摘要： A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node. A cross-coupled switching element comprising a second P-channel IGFET has its gate connected to the complementary data output node and is arranged to selectively connect the data storage node to the voltage supply node. A third P-channel IGFET has its channel arranged to selectively connect the data storage node to the voltage supply node when the cell is disabled. A second N-channel IGFET is arranged to selectively connect the data storage node to the data input node. A high impedance leakage current discharge path electrically connects the data storage node to the one voltage supply node, and discharges any leakage current on the data storage node. The high impedance leakage current discharge path may take a variety of forms, and need not comprise a discrete resistor.

摘要翻译： 在一个实施例中，用于静态触发器应用的五晶体管CMOS静态锁存单元包括具有数据输入节点，数据存储节点，互补数据输出节点，时钟输入节点，用于选择性地使能或 不启用电池，以及一对电源供应节点。 基本上标准的CMOS反相器具有连接到互补数据输出节点的输出。 反相器包括互补的IGFET对，即N沟道IGFET和P沟道IGFET。 N沟道反相器IGFET的通道选择性地将互补数据输出节点电连接到地。 P沟道反相器IGFET的通道选择性地将互补数据输出节点电连接到电压供应节点。 逆变器晶体管栅电极连接到数据存储节点。 包括第二P沟道IGFET的交叉耦合开关元件的栅极连接到互补数据输出节点并被布置成有选择地将数据存储节点连接到电压供应节点。 第三P沟道IGFET具有其通道，其布置成在单元被禁用时选择性地将数据存储节点连接到电压供应节点。 第二N沟道IGFET被布置成选择性地将数据存储节点连接到数据输入节点。 高阻抗泄漏电流放电路径将数据存储节点电连接到一个电压供应节点，并且在数据存储节点上放电任何漏电流。 高阻抗漏电流放电路径可以采取各种形式，并且不需要包括分立电阻器。

公开(公告)号：US5561429A

公开(公告)日：1996-10-01

申请号：US852877

申请日：1986-04-16

申请人： M. Halberstam ,  James E. Meister ,  Moshe Mazin ,  Dennis A. Henlin ,  Jun-ichi Sano ,  Edward T. Lewis

发明人： M. Halberstam ,  James E. Meister ,  Moshe Mazin ,  Dennis A. Henlin ,  Jun-ichi Sano ,  Edward T. Lewis

IPC分类号： G06F17/30 ,  G11C15/00 ,  G06F7/02

CPC分类号： G06F17/30982 ,  G11C15/00

摘要： A content limit addressable memory (CLAM) having a plurality of lower and upper limits stored therein for comparison to corresponding subfields of an input word. Each corresponding upper and lower limit forms a bracket. Corresponding brackets form a window. The brackets correspond to the subfields and are of the same number of bits. The brackets and subfields are alterable in width to allow each bracket and subfield to have any number of bits in multiples of two. A valid match of the input word with any window can occur with any combination of the brackets of a window matching or not matching the corresponding subfields of the input word. A plurality of outputs corresponding to each of the windows indicates a match of the corresponding window to the input word. Additionally, the CLAM can compare data stored therein against an applied window with the matching operations as described above.

摘要翻译： 存储有多个下限和上限的内容限制可寻址存储器（CLAM），用于与输入字的相应子字段进行比较。 每个对应的上限和下限形成一个支架。 相应的括号形成一个窗口。 括号对应于子字段并且具有相同的位数。 括号和子字段的宽度是可变的，以允许每个括号和子字段具有任意数量的二进制数。 输入字与任何窗口的有效匹配可以与匹配或不匹配输入字的相应子字段的窗口的括号的任意组合发生。 对应于每个窗口的多个输出表示对应的窗口与输入单词的匹配。 此外，CLAM可以将如上所述的匹配操作来比较存储在其中的数据与应用的窗口。

公开(公告)号：US4472821A

公开(公告)日：1984-09-18

申请号：US374587

申请日：1982-05-03

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： G11C19/18 ,  G11C19/28 ,  H03K17/04 ,  H03K17/687 ,  H03K19/017

CPC分类号： G11C19/184

摘要： A shift register using dual gate transistors is described. Each stage consists of a P-channel and and N-channel dual gate transistor interconnected to provide both an inverting function and a switching function. The gates of each stage of one set of alternate stages are clocked in one phase with a clocking voltage alternating between a low level and a high level and its inverse. The gates of each stage of the other set of alternative stages are clocked in the opposite phase with the clocking voltage and its inverse.

摘要翻译： 描述使用双栅极晶体管的移位寄存器。 每个级由互连的P沟道和N沟道双栅极晶体管组成，以提供反相功能和开关功能。 一组交替级的每个级的门在一个相位中以在低电平和高电平之间交替的时钟电压及其反相来计时。 另一组替代级的每个级的门以与时钟电压及其相反的相反相位计时。

公开(公告)号：US4419741A

公开(公告)日：1983-12-06

申请号：US299343

申请日：1981-09-04

申请人： Roger G. Stewart ,  Moshe Mazin

发明人： Roger G. Stewart ,  Moshe Mazin

IPC分类号： G11C17/06 ,  H01L27/12 ,  G11C5/06

CPC分类号： H01L27/12 ,  G11C17/06

摘要： The ROM utilizes a diode x-y memory array which can be comprised of a number of suitable materials which form rectifying junctions. The diodes are formed vertically in order to provide a very high density array. On pitch decoder circuitry which is capable of matching the high density of the memory cells in the x-y memory array is also described, as is a unique apparatus for joining adjacent ends of conductive lines which are spaced very close together without increasing their pitch.

摘要翻译： ROM使用二极管x-y存储器阵列，其可以由形成整流结的许多合适的材料组成。 二极管垂直形成，以提供非常高密度的阵列。 还描述了能够匹配x-y存储器阵列中的高密度存储器单元的音调解码器电路，作为用于连接非常靠近在一起而不增加它们的音调的导线的相邻端的独特设备。

公开(公告)号：US4704701A

公开(公告)日：1987-11-03

申请号：US667198

申请日：1984-11-01

申请人： Moshe Mazin ,  Edward T. Lewis

发明人： Moshe Mazin ,  Edward T. Lewis

IPC分类号： G06F7/50 ,  G06F7/507 ,  G06F7/508

CPC分类号： G06F7/507 ,  G06F2207/3876

摘要： A multibit digital adder wherein a proper carry-out signal is generated simultaneously in different parts of such adder.

摘要翻译： 一种多位数字加法器，其中在这种加法器的不同部分中同时产生适当的进位信号。

公开(公告)号：US4499558A

公开(公告)日：1985-02-12

申请号：US464099

申请日：1983-02-04

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： G11C11/412 ,  H01L27/092 ,  H01L27/11 ,  G11C11/40

CPC分类号： G11C11/412 ,  H01L27/0925 ,  H01L27/11 ,  H01L27/1104

摘要： A five-transistor CMOS static random-access memory cell which does not require a voltage on the address line higher than the supply voltage to effect writing, and so may be fabricated employing CMOS technology on a bulk single-crystal semiconductor substrate. The cell includes a latch comprising a complementary pair of IGFETs for actively storing one binary logic state. For storing the other binary logic state, there is only a single pull-up transistor connected to one data node and a high-impedance leakage current discharge path for the other data node. The cell also includes a pair of input/output gating transistors connected to the data nodes and operating in push-pull. Various forms of high impedance leakage current discharge path are disclosed, none of which require any increase in chip area. In one form, the high-impedance current discharge path comprises an IGFET having its gate tied to its drain terminal and having a channel extending between device regions which exist on the chip in any event for other purposes. In another form, a reverse-biased PN junction diode included in one of the gating transistors has sufficient conductivity to discharge leakage current to ground.

摘要翻译： 一种五晶体管CMOS静态随机存取存储单元，其不需要高于电源电压的地址线上的电压来进行写入，因此可以在大容量单晶半导体衬底上采用CMOS技术制造。 该单元包括一个锁存器，其包括用于主动地存储一个二进制逻辑状态的互补对IGFET。 为了存储另一个二进制逻辑状态，只有一个上拉晶体管连接到一个数据节点和另一个数据节点的高阻抗泄漏电流放电路径。 电池还包括一对连接到数据节点的输入/输出选通晶体管，并以推挽方式工作。 公开了各种形式的高阻抗泄漏电流放电路径，其中没有一个需要芯片面积的增加。 在一种形式中，高阻抗电流放电路径包括IGFET，其栅极连接到其漏极端子，并且在任何情况下存在于芯片上的器件区域之间延伸的沟道用于其它目的。 在另一种形式中，包括在一个门控晶体管中的反向偏置PN结二极管具有足够的导电性，以将漏电流放电到地。