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    Associative cache memory capable of reconfiguring a K-way and N-set cache memory into a M-unit, K-way and N/M-set cache memory
    2.
    发明授权
    Associative cache memory capable of reconfiguring a K-way and N-set cache memory into a M-unit, K-way and N/M-set cache memory 有权
    能够将K路和N组高速缓冲存储器重构为M单元，K路和N / M集高速缓冲存储器的关联高速缓冲存储器

    公开(公告)号：US06317351B2

    公开(公告)日：2001-11-13

    申请号：US09800685

    申请日：2001-03-07

    申请人： Hoon Choi ,  Myung-Kyoon Yim

    发明人： Hoon Choi ,  Myung-Kyoon Yim

    IPC分类号： G11C1504

    CPC分类号： G11C15/04 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A K way cache memory having improved operational speed and reduced power consumption is provided. The cache memory includes M cache memory units, but only activates one of the units at a given time. Moreover, only one match line is activated corresponding to a way having a tag address that matches an externally provided tag address.

    摘要翻译： 提供了具有改进的操作速度和降低的功耗的K路缓存存储器。 高速缓冲存储器包括M个高速缓冲存储器单元，但仅在给定时间激活其中一个单元。 此外，只有一个匹配行被激活，对应于具有与外部提供的标签地址匹配的标签地址的方式。

    Method and apparatus for reducing power consumption by skipping second accesses to previously accessed cache lines
    3.
    发明授权
    Method and apparatus for reducing power consumption by skipping second accesses to previously accessed cache lines 失效
    通过跳过对先前访问的高速缓存行的第二次访问来降低功耗的方法和装置

    公开(公告)号：US06560679B2

    公开(公告)日：2003-05-06

    申请号：US09742030

    申请日：2000-12-20

    申请人： Hoon Choi ,  Myung-Kyoon Yim

    发明人： Hoon Choi ,  Myung-Kyoon Yim

    IPC分类号： G06F1208

    CPC分类号： G06F12/0882 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.

    摘要翻译： 提供了一种数字数据处理系统，其包括数字数据处理器，具有标签RAM和数据RAM的高速缓冲存储器，以及用于控制对高速缓存存储器的访问的控制器。 控制器存储关于与最近访问标签RAM相关联的访问类型，操作模式和高速缓存命中/错误的状态信息，并且基于状态信息控制刚刚在上述访问之后的标签RAM的当前访问 用于第二次访问的主存储器地址的设置字段。 控制器基于状态信息和用于第二次访问的主存储器地址的设置字段的一部分来确定当前访问是应用于在第一访问中访问的相同高速缓存行，并且允许当前访问是 当当前访问应用于在上一次访问中访问的同一个高速缓存行时跳过。