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公开(公告)号：US20180285733A1
公开(公告)日：2018-10-04
申请号：US15476998
申请日：2017-04-01
摘要： Technologies for artificial neural network training include a computing node with a host fabric interface that sends a message that includes one or more artificial neural network training algorithm values to another computing node in response to receipt of a request to send the message. Prior to sending the message, the host fabric interface may receive a request to quantize the message and quantize the message based on a quantization level included in the request to generate a quantized message. The quantization message includes one or more quantized values such that each quantized value has a lower precision than a corresponding artificial neural network training algorithm value. The host fabric interface then transmits the quantized message, which includes metadata indicative of the quantization level, to another computing node in response to quantization of the message for artificial neural network training. Other embodiments are described and claimed.
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公开(公告)号：US20160239065A1
公开(公告)日：2016-08-18
申请号：US14621731
申请日：2015-02-13
申请人： VICTOR W. LEE , DAEHYUN KIM , YUXIN BAI , SHIHAO JI , SHENG LI , DHIRAJ D. KALAMKAR , NAVEEN K. MELLEMPUDI
发明人： VICTOR W. LEE , DAEHYUN KIM , YUXIN BAI , SHIHAO JI , SHENG LI , DHIRAJ D. KALAMKAR , NAVEEN K. MELLEMPUDI
CPC分类号： G06F1/324 , G06F1/3293 , G06F1/3296 , G06F9/5088 , G06F9/5094 , Y02D10/124 , Y02D10/126 , Y02D10/172 , Y02D10/22 , Y02D10/32
摘要： In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器用于独立地执行指令的多个核心，所述核心包括存储性能信息的多个计数器以及耦合到所述多个核心的功率控制器，所述功率控制器具有从其中接收性能信息的逻辑 至少部分地基于性能信息和模型信息来确定多个计数器中的一些，以确定要激活的核心数量和用于下一个操作间隔的核心数量的性能状态，并且引起核心数量 在下一个操作间隔期间处于活动状态，所述性能信息与所述多个核心中的一个或多个核心上的工作负载的执行相关联。 描述和要求保护其他实施例。
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公开(公告)号：US20160239074A1
公开(公告)日：2016-08-18
申请号：US14621709
申请日：2015-02-13
申请人： VICTOR W. LEE , EDWARD T. GROCHOWSKI , DAEHYUN KIM , YUXIN BAI , SHENG LI , NAVEEN K. MELLEMPUDI , DHIRAJ D. KALAMKAR
发明人： VICTOR W. LEE , EDWARD T. GROCHOWSKI , DAEHYUN KIM , YUXIN BAI , SHENG LI , NAVEEN K. MELLEMPUDI , DHIRAJ D. KALAMKAR
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F1/329 , G06F1/3296 , G06F9/50 , Y02D10/126 , Y02D10/14 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括：多个第一核，用于独立地执行指令，所述多个第一核中的每一个包括存储执行信息的多个计数器; 用于执行存储器操作的至少一个第二核心; 以及功率控制器，用于从所述多个计数器中的至少一些计数器接收性能信息，至少部分地基于所述性能信息确定在所述处理器上执行的工作负载类型，并且基于所述工作负载类型，动态地从一个或多个计算机迁移一个或多个线程 或多个第一核心到至少一个第二核心，以在下一个操作间隔期间执行。 描述和要求保护其他实施例。
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