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8 条记录 (耗时 0.009 秒)

    High speed controller area network receiver having improved EMI immunity
    1.
    发明申请
    High speed controller area network receiver having improved EMI immunity 有权

    公开(公告)号：US20060160511A1

    公开(公告)日：2006-07-20

    申请号：US11317972

    申请日：2005-12-23

    申请人： Narasimhan Trichy ,  Wayne Chen

    发明人： Narasimhan Trichy ,  Wayne Chen

    IPC分类号： H04B1/06 ,  H04B7/00

    CPC分类号： H04L25/0276 ,  G06F13/4072 ,  H04L12/40013 ,  H04L12/40032 ,  H04L2012/40215 ,  H04L2012/40273

    摘要： A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver includes a voltage divider network connected to a front-end amplifier for dividing down the input signal from a two wire line by a predetermined amount and amplifying the signal by the same predetermined amount. The front-end amplifier generates the common-mode voltage of the input signal for a reference generator that determines the logic level of the incoming signal and subtracts a bandgap voltage reference from the common-mode voltage. A comparator compares the difference between the output of the front-end amplifier and the resultant signal generated by the reference generator to generate an output signal for the receiver. This CAN receiver architecture is faster than conventional designs and possesses an improved common-mode rejection, while operating over a wide input common mode range.

    Process, supply, and temperature insensitive integrated time reference circuit
    4.
    发明授权
    Process, supply, and temperature insensitive integrated time reference circuit 有权
    过程，供应和温度不敏感的集成时间参考电路

    公开(公告)号：US07598822B2

    公开(公告)日：2009-10-06

    申请号：US11100783

    申请日：2005-04-07

    申请人： Narasimhan Trichy Rajagopal ,  Patrick Peter Siniscalchi

    发明人： Narasimhan Trichy Rajagopal ,  Patrick Peter Siniscalchi

    IPC分类号： H03L1/00

    CPC分类号： H03K3/011 ,  H03K3/0231

    摘要： Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.

    摘要翻译： 公开了精密集成时间参考电路。 优选实施例提供对过程，供应和温度变化相对不敏感的时间参考电路。 公开了本发明的优选实施例，其中根据本发明的张弛振荡器包括被配置为将参考电压与实际电路电阻值成比例地保持的参考电压电路。 本发明的方面还包括温度变化的动态补偿。

    Self correcting scheme to match pull up and pull down devices
    5.
    发明申请
    Self correcting scheme to match pull up and pull down devices 有权
    自校正方案，以配合拉拔设备

    公开(公告)号：US20060022735A1

    公开(公告)日：2006-02-02

    申请号：US10901833

    申请日：2004-07-27

    申请人： Wayne Chen ,  Narasimhan Trichy

    发明人： Wayne Chen ,  Narasimhan Trichy

    IPC分类号： H03H11/26

    CPC分类号： H03K19/00323 ,  H03K2005/00097 ,  H03K2005/00123 ,  H04L25/0272

    摘要： The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having an input coupled to an output of the first comparator; a second flip flop having an input coupled to an output of the second comparator; a counter having inputs coupled to the first and second flip flops; and a delay device controlled by an output of the counter, wherein the delay device provides a pull down control signal that is delayed relative to a pull up control signal.

    摘要翻译： 匹配上拉和下拉器件的自校正方案包括：用于将共模信号与高参考极限进行比较的第一比较器; 第二比较器，用于将共模信号与低参考极限进行比较; 第一触发器，其具有耦合到所述第一比较器的输出的输入; 第二触发器，具有耦合到第二比较器的输出的输入; 具有耦合到第一和第二触发器的输入的计数器; 以及由计数器的输出控制的延迟装置，其中延迟装置提供相对于上拉控制信号延迟的下拉控制信号。

    Differential signal receiver and method
    6.
    发明申请
    Differential signal receiver and method 有权
    差分信号接收机和方法

    公开(公告)号：US20060019619A1

    公开(公告)日：2006-01-26

    申请号：US10898272

    申请日：2004-07-23

    申请人： Mohammad Al-Shyoukh ,  Narasimhan Trichy

    发明人： Mohammad Al-Shyoukh ,  Narasimhan Trichy

    IPC分类号： H03B1/00

    CPC分类号： H03F3/45076

    摘要： A differential signal receiver and method is disclosed. One embodiment relates to a receiver for receiving a differential signal. The receiver includes a first voltage-to-current converter that converts the voltage received at a first input to a first current, and a second voltage-to-current converter that converts a voltage signal received at a second input to a second current. A current subtractor provides a difference current of the first and second currents that is indicative of the differential signal.

    摘要翻译： 公开了一种差分信号接收机和方法。 一个实施例涉及用于接收差分信号的接收机。 接收器包括将在第一输入处接收的电压转换为第一电流的第一电压 - 电流转换器，以及将在第二输入处接收的电压信号转换为第二电流的第二电压 - 电流转换器。 电流减法器提供表示差分信号的第一和第二电流的差分电流。

    High frequency balanced phase interpolator
    8.
    发明授权
    High frequency balanced phase interpolator 有权
    高频平衡相位内插器

    公开(公告)号：US07196564B2

    公开(公告)日：2007-03-27

    申请号：US11187412

    申请日：2005-07-22

    申请人： Narasimhan Trichy Rajagopal ,  Bradley A. Kramer

    发明人： Narasimhan Trichy Rajagopal ,  Bradley A. Kramer

    IPC分类号： H03K3/00

    CPC分类号： H03K5/13

    摘要： A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an output and a second portion of the first modulated input signal to an internal balancing node. The weighting system also is configured to steer a first portion of the second modulated input signal to the output and a second portion of the second modulated input signal to the balancing node. The first portion of the first and second modulated input signals are summed at the output to provide an interpolated output signal having a phase angle that is between the first and second phase angles.

    摘要翻译： 相位插值系统包括输入级，其提供具有选定的第一和第二相对相位角的第一和第二调制输入信号。 加权系统被配置为将第一调制输入信号的第一部分引导到第一调制输入信号的输出和第二部分到内部平衡节点。 加权系统还被配置为将第二调制输入信号的第一部分引导到输出端，并将第二调制输入信号的第二部分转向平衡节点。 第一和第二调制输入信号的第一部分在输出处相加以提供具有在第一和第二相位角之间的相位角的内插输出信号。