公开(公告)号：US20100156434A1

公开(公告)日：2010-06-24

申请号：US12646736

申请日：2009-12-23

申请人： Noboru OKINO ,  Masumi Okino

发明人： Noboru OKINO ,  Masumi Okino

IPC分类号： G01R31/02 ,  H01H31/02

CPC分类号： H01L21/67178 ,  G01R31/2831 ,  G01R31/2886 ,  G01R31/2893 ,  H01L21/67253 ,  H01L21/67748

摘要： There is provided a testing apparatus including a plurality of test units, a storage that is shared by the plurality of test units, where the storage stores therein wafers under test to be tested by the plurality of test units, a transport mechanism that transports the wafers under test between the storage and each of the plurality of test units, a mainframe that specifies a test procedure for each of the plurality of test units, a power source that is shared by the plurality of test units, where the power source supplies power to each of the plurality of test units, and a pressure source that is shared by the plurality of test units, where the pressure source supplies a pressure to each of the plurality of test units. Here, each of the plurality of test units includes a test module that transmits and receives a test signal to/from a plurality of circuits formed on a wafer under test, a connector that connects together transmission paths of the test signal between the test module and the wafer under test, a holding member that brings the wafer under test into contact with the connector when supplied with the pressure, and a housing that houses therein the holding member and the connector, where the wafer under test is to be tested within the housing.

摘要翻译： 提供了一种包括多个测试单元的测试装置，由多个测试单元共享的存储器，其中存储器在其中存储待测试的晶片以由多个测试单元测试，传送机构，其传送晶片 在所述存储器和所述多个测试单元中的每一个之间进行测试，指定所述多个测试单元中的每一个测试单元的测试过程的主机，由所述多个测试单元共享的电源，其中所述电源向 所述多个测试单元中的每一个以及由所述多个测试单元共享的压力源，其中所述压力源向所述多个测试单元中的每一个提供压力。 这里，多个测试单元中的每个测试单元包括测试模块，该测试模块向被测试晶片上形成的多个电路发送和接收测试信号，连接器将测试模块与测试模块之间的测试信号的传输路径相连， 被测试的晶片，当被供给压力时使待测晶片与连接器接触的保持构件以及容纳保持构件和连接器的壳体，其中待测试的晶片将在壳体内被测试 。

公开(公告)号：US5140176A

公开(公告)日：1992-08-18

申请号：US666001

申请日：1991-03-07

申请人： Noboru Okino

发明人： Noboru Okino

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G05B19/042 ,  G06F11/22

CPC分类号： G05B19/0423 ,  G01R31/318541

摘要： A logic circuit part, which is composed of a flip-flop group and a combinational circuit and performs a sequential logic operation, is added with a specify circuit for selectively specifying desired flip-flop circuits in the flip-flop group and a write circuit for applying a set or reset signal to the flip-flop circuits selectively specified by the specify circuit. Each flip-flop circuit includes: a flip-flop for writing input data in response to a system clock; a first AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the set signal to set the flip-flop; a second AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the reset signal to reset the flip-flop; and a third and gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the output logic of the flip-flop to the outside.

公开(公告)号：US4670879A

公开(公告)日：1987-06-02

申请号：US702256

申请日：1985-02-15

申请人： Noboru Okino

发明人： Noboru Okino

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/319 ,  G06F11/22

CPC分类号： G01R31/31921 ,  G01R31/31908

摘要： In a main pattern memory are stored an increment command pattern and an enable control pattern in addition to test patterns. The main pattern memory is read out with an address from an address control circuit. The increment command pattern thus read out of the main pattern memory instructs incrementing of an address pointer, and a partial pattern memory is read out according to the contents of the address pointer. In accordance with the enable control pattern read out of the main pattern memory, a gate circuit is controlled to open, through which the output of the partial pattern memory is passed, and bits of the passed output are each ORed, by an OR circuit, with the corresponding bits of the test pattern read out of the main pattern memory, providing the ORed output as a test pattern.

摘要翻译： 在主图案存储器中除了测试图案之外还存储增量命令模式和使能控制模式。 使用地址控制电路的地址读出主模式存储器。 因此，从主模式存储器读出的增量命令模式指示地址指针的递增，并且根据地址指针的内容读出部分模式存储器。 根据从主模式存储器读出的使能控制模式，通过OR电路控制门电路打开部分模式存储器的输出，并通过输出的位， 测试模式的相应位从主模式存储器中读出，提供ORed输出作为测试模式。

公开(公告)号：US06877118B2

公开(公告)日：2005-04-05

申请号：US09844301

申请日：2001-04-27

申请人： Hiromi Oshima ,  Noboru Okino ,  Yasuhiro Kawata

发明人： Hiromi Oshima ,  Noboru Okino ,  Yasuhiro Kawata

IPC分类号： G01R31/28 ,  G06F11/22 ,  G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/44 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/82

摘要： A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped. In addition, a decision is rendered that, when the number of failure memory cells on the same address line reaches a predetermined number, such address line is a bad address line, and after such decision has rendered, the test of memory cells on the bad address line is substantially not effected.

摘要翻译： 提供了可以在短时间内测试闪存的存储器测试方法和装置。 在测试具有块功能的闪速存储器的情况下，在存储器测试方法和其中将预定逻辑值写入构成存储器的每个块的存储器单元的装置中，从存储器单元读出写入的逻辑值以进行比较 具有期望值，并且当读出的逻辑值和期望值彼此不一致时，这样的存储单元是故障存储器单元，则判定当故障存储器的数量 每个块中的单元达到预定数量，该块是坏块，并且该块的测试被停止。 此外，作出判定，当相同地址线上的故障存储单元的数量达到预定数量时，这样的地址线是不好的地址线，并且在这样做的决定之后，对坏的存储器单元的测试 地址线基本上不受影响。

公开(公告)号：US5410687A

公开(公告)日：1995-04-25

申请号：US159704

申请日：1993-12-01

申请人： Kenichi Fujisaki ,  Noboru Okino

发明人： Kenichi Fujisaki ,  Noboru Okino

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/40 ,  G11C29/44 ,  G06F11/00

CPC分类号： G11C29/72

摘要： A failure analysis of a semiconductor memory compares data written into and out of each cell of the semiconductor memory. When there is a disagreement, a "1" is written into a failure analysis memory. A disagreement signal is applied as a write command to column and row address fail count memories and is counted by a fail counter. The column address and row address fail count memories receive the column and row addresses, respectively. When the write command is applied to the column and row address fail count memories, the number of defective cells is read out of the memory addresses by a read modify write operation. A 1 is added by column and row adders to the number of defective cells read out, and the results are written into the column and row address fail count memories. The number of defective cells is read out of the column address fail count memory and compared with a number of row spare lines of the memory under test. When the former is greater than the latter, the column address is decided as a failing address line, is counted by a failing address line counter and is written into a failing address memory. The row address is sequentially changed, beginning with a 0, at each failing column address when a "1" is read out of the failure analysis memory. The contents of the memories are each rewritten by subtracting a 1 therefrom and the fail counter is decremented by one.

摘要翻译： 半导体存储器的故障分析比较写入和移出半导体存储器的每个单元的数据。 当有不同意见时，将“1”写入故障分析存储器。 不同意信号作为写入命令应用于列和行地址故障计数存储器，并由故障计数器计数。 列地址和行地址故障计数存储器分别接收列和行地址。 当写入命令被应用于列和行地址故障计数存储器时，通过读修改写操作从存储器地址中读出有缺陷单元的数量。 通过列和行加法器将A 1添加到读出的有缺陷单元的数量，并将结果写入列和行地址故障计数存储器。 从列地址故障计数存储器中读出有缺陷单元的数量，并将其与被测存储器的多行行备用线进行比较。 当前者大于后者时，列地址被确定为故障地址线，由故障地址行计数器进行计数，并写入失败的地址存储器。 当从故障分析存储器中读出“1”时，在每个故障列地址处，行地址从0开始顺序更改。 存储器的内容通过从其中减去1来重写，并且将故障计数器递减1。

公开(公告)号：US08207744B2

公开(公告)日：2012-06-26

申请号：US12646736

申请日：2009-12-23

申请人： Noboru Okino ,  Masumi Okino, legal representative

发明人： Noboru Okino

IPC分类号： G01R31/02

CPC分类号： H01L21/67178 ,  G01R31/2831 ,  G01R31/2886 ,  G01R31/2893 ,  H01L21/67253 ,  H01L21/67748

摘要： There is provided a testing apparatus including a plurality of test units, a storage that is shared by the plurality of test units, where the storage stores therein wafers under test to be tested by the plurality of test units, a transport mechanism that transports the wafers under test between the storage and each of the plurality of test units, a mainframe that specifies a test procedure for each of the plurality of test units, a power source that is shared by the plurality of test units, where the power source supplies power to each of the plurality of test units, and a pressure source that is shared by the plurality of test units, where the pressure source supplies a pressure to each of the plurality of test units. Here, each of the plurality of test units includes a test module that transmits and receives a test signal to/from a plurality of circuits formed on a wafer under test, a connector that connects together transmission paths of the test signal between the test module and the wafer under test, a holding member that brings the wafer under test into contact with the connector when supplied with the pressure, and a housing that houses therein the holding member and the connector, where the wafer under test is to be tested within the housing.

摘要翻译： 提供了一种包括多个测试单元的测试装置，由多个测试单元共享的存储器，其中存储器在其中存储待测试的晶片以由多个测试单元测试，传送机构，其传送晶片 在所述存储器和所述多个测试单元中的每一个之间进行测试，指定所述多个测试单元中的每一个的测试过程的主机，由所述多个测试单元共享的电源，其中所述电源向 所述多个测试单元中的每一个以及由所述多个测试单元共享的压力源，其中所述压力源向所述多个测试单元中的每一个提供压力。 这里，多个测试单元中的每个测试单元包括测试模块，该测试模块向被测试晶片上形成的多个电路发送和接收测试信号，连接器将测试模块与测试模块之间的测试信号的传输路径相连， 被测试的晶片，当被供给压力时使待测晶片与连接器接触的保持构件以及容纳保持构件和连接器的壳体，其中待测试的晶片将在壳体内被测试 。

公开(公告)号：US06836863B2

公开(公告)日：2004-12-28

申请号：US09925138

申请日：2001-08-08

申请人： Makoto Tabata ,  Noboru Okino

发明人： Makoto Tabata ,  Noboru Okino

IPC分类号： G11C2900

CPC分类号： G11C16/3445 ,  G11C16/344 ,  G11C29/52

摘要： A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count FN is equal to or greater than a given number TF, a plurality of erasure operations are conducted consecutively next. If FN

摘要翻译： 存储器块通过批处理操作进行擦除操作。 随后，对存储器块进行读出测试，以对未存储单元的数量进行计数。 如果计数FN等于或大于给定数量TF，则接下来进行多次擦除操作。 如果FN