公开(公告)号：US4413339A

公开(公告)日：1983-11-01

申请号：US277060

申请日：1981-06-24

Applicant: Charles M. Riggle ,  Lih-Jyh Weng ,  Norman A. Field

Inventor： Charles M. Riggle ,  Lih-Jyh Weng ,  Norman A. Field

IPC: H03M13/15 ,  G06F11/12

CPC classification number: H03M13/151

Abstract: An error detecting and correcting system implementing the Reed-Solomon (1023, 1006) code having code words whose symbols are elements in the Galois field GF(2.sup.10) generated by either the primitive polynomial x.sup.10 +x.sup.3 +1 or x.sup.10 +x.sup.7 +1. An original data word is encoded to produce a code word w(x) including a first set of checksum symbols appended thereto. Upon retrieval, the data symbols of the receive code word y(x) are encoded by the same encoder that encodes the original data word to produce a second set of checksum symbols. Both sets of checksum symbols are modulo-two summed to produce a residue R(x) from which error syndromes S.sub.i can be computed and thus enable rapid correction of errors in the received code word y(x). The system also monitors the number of non-zero symbols in the residue R(x) in order to avoid unnecessary computation of error syndromes S.sub.i and other decoding routines, such as when the received code word y(x) is otherwise uncorrectable or when the error exists only in the received checksum symbols, rather than in the data symbols. The distance between code words being (2T+ 2), the error correction routine is bypassed when the number of non-zero symbols in R(x) is less than or equal to T, which indicates that errors only reside in the checksum symbols. When the number of non-zero symbols equals (T+1), the error is uncorrectable. For determining whether a single error exists so that correction can quickly be made, the system also tests whether S.sub.i+1 /S.sub.i is constant for all error syndromes S.sub.i.

Abstract translation: 实现具有代码字的Reed-Solomon（1023,1006）代码的错误检测和校正系统，其码元是由原始多项式x10 + x3 + 1或x10 + x7 + 1产生的伽罗瓦域GF（210）中的元素。 原始数据字被编码以产生包括附加到其上的第一组校验和符号的码字w（x）。 在检索时，接收码字y（x）的数据符号由编码原始数据字的相同编码器编码，以产生第二组校验和符号。 两组校验和符号被模二相加以产生残差R（x），从中可以计算出错误综合征Si，从而能够快速校正接收到的代码字y（x）中的错误。 该系统还监视残差R（x）中的非零符号的数目，以避免误差综合征Si和其他解码程序的不必要的计算，例如当接收到的代码字y（x）不可校正时或当 错误仅存在于接收到的校验和符号中，而不是数据符号中。 当R（x）中的非零符号数小于或等于T时，代码字之间的距离为（2T + 2），纠错程序被旁路，这表示错误仅驻留在校验和符号中。 当非零符号的数量等于（T + 1）时，该错误是不可校正的。 为了确定是否存在单一误差以便能够快速进行校正，系统还测试Si + 1 / Si对于所有误差综合征Si是否恒定。

公开(公告)号：US4484142A

公开(公告)日：1984-11-20

申请号：US375932

申请日：1982-05-07

Applicant: Bernardo Rub ,  Norman A. Field

Inventor： Bernardo Rub ,  Norman A. Field

IPC: G11B20/14 ,  H03K5/26 ,  H03L7/085 ,  H03K5/135

CPC classification number: G11B20/1419 ,  H03K5/26 ,  H03L7/085

Abstract: The present invention includes a first input signal circuit to receive pulse signals from a voltage-controlled oscillator (VCO), or some other controllable pulse signal source, and a second input signal circuit to receive pulse signals from a magnetic recording medium, or some pulse signal source, with which the voltage controlled oscillator is to be put in phase synchronization. A correction signal generator circuit is connected to both the input signal circuits to provide a first correction signal in response to a pulse signal from the recording medium and to provide a second correction signal in response to a pulse signal from the VCO. There is a third circuit which monitors how long a correction signal is in effect and if such a correction signal is present for longer than a predetermined time, the third circuit terminates the correction signal to enable a new correction signal to be generated in response to the next one of said input signals to arrive. Finally, there is a fourth circuit which is connected to the correction circuitry to permit it, in a first mode of operation, to be enabled at all times to phase correct the controllable pulse signal source in response to a predetermined pattern of signals from the recording medium and to permit it, in a second mode of operation, to be available only during "window" periods initiated by pulse signals from the recording medium.

Abstract translation: 本发明包括用于接收来自压控振荡器（VCO）的脉冲信号的第一输入信号电路或一些其它可控脉冲信号源，以及用于从磁记录介质接收脉冲信号的第二输入信号电路，或一些脉冲 信号源，使压控振荡器与其进行相位同步。 校正信号发生器电路连接到两个输入信号电路，以响应于来自记录介质的脉冲信号提供第一校正信号，并响应于来自VCO的脉冲信号提供第二校正信号。 存在监视校正信号有效多长时间的第三电路，并且如果这种校正信号存在长于预定时间，则第三电路终止校正信号以使得能够响应于该校正信号产生新的校正信号 所述输入信号中的下一个到达。 最后，存在连接到校正电路的第四电路，以允许其在第一操作模式下始终使能以响应于来自记录的预定信号模式来相位校正可控脉冲信号源 并且允许其在第二操作模式下仅在由来自记录介质的脉冲信号启动的“窗口”期间可用。

公开(公告)号：US3982194A

公开(公告)日：1976-09-21

申请号：US550693

申请日：1975-02-18

Applicant: Chao S. Chi ,  Peter T. McLean ,  Norman A. Field

Inventor： Chao S. Chi ,  Peter T. McLean ,  Norman A. Field

IPC: H04L7/033 ,  H03B3/04 ,  H03K5/18

CPC classification number: H04L7/033

Abstract: In a feedback control system wherein data pulses also establish timing coordination between the data and the processing devices, two delay circuits are provided to extract the synchronized clock pulses from the coded incoming signal. This enables relative digital decoding and ensures a precise data transfer to a computer interface. One of the delay circuits enables a data reconditioner circuit to buffer the data and eliminates data peak shifting. The reconditioned data is provided to a coincident circuit which selectively transfers the data to a computer interface and to a phase difference detector. The other delay circuit provides to the phase difference detector a second input corresponding in time to the coded incoming data pulses. The detector's output generates a DC error voltage which synchronizes a voltage controlled oscillator (VCO). The outputs of the VCO are clock pulses in phase with the coded incoming signals. The feedback control system is capable of operating over a range of frequencies without effecting the margin for peak shifting.

Abstract translation: 在其中数据脉冲也建立数据和处理装置之间的时序协调的反馈控制系统中，提供两个延迟电路以从编码的输入信号提取同步的时钟脉冲。 这使得能够进行相对数字解码并确保将精确的数据传输到计算机接口。 其中一个延迟电路使得数据重新调节器电路缓冲数据并消除数据峰值偏移。 修复后的数据被提供给一个重合的电路，该电路有选择地将数据传送到计算机接口和相位差检测器。 另一个延迟电路向相位差检测器提供对应于编码的输入数据脉冲的时间上的第二输入。 检测器的输出产生一个同步压控振荡器（VCO）的直流误差电压。 VCO的输出是与编码的输入信号同相的时钟脉冲。 反馈控制系统能够在一定频率范围内工作，而不影响峰值偏移的余量。