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公开(公告)号：US09722648B2
公开(公告)日：2017-08-01
申请号：US13985990
申请日：2011-03-01
CPC分类号： H04B1/06 , H04L25/0262
摘要： An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.
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2.发明申请INTEGRATED CALIBRATION CIRCUIT AND A METHOD FOR CALIBRATION OF A FILTER CIRCUIT 审中-公开集成校准电路和滤波电路校准方法公开(公告)号：US20160233846A1
公开(公告)日：2016-08-11
申请号：US15022239
申请日：2013-09-27
CPC分类号： H03H7/0161 , G01S7/032 , H03H7/12 , H03H2210/028 , H03H2210/036 , H03H2210/04 , H03H2210/043
摘要： A calibration circuit and a method for calibrating a RC circuit, such as a high-pass filter, of an integrated circuit are provided. The calibration circuit comprises a filter arrangement having tuneable filter for filtering an input signal having a predetermined frequency. The filter comprises tuneable resistor elements, a saturation detector for detecting saturation and non-saturation of the tuneable filter by comparing a comparison voltage with the signal voltage of the filtered input signal, calibration control logic for providing incrementing and decrementing counter signals. The calibration circuit sets the comparison voltage to a first threshold voltage provides iteratively the incrementing counter signal to the filter until saturation is detected reduces the comparison voltage to a predetermined second threshold voltage after saturation is detected, the second threshold voltage being a lower value than the first threshold voltage, and provides the decrementing counter signal to the filter until non-saturation is detected.
摘要翻译： 提供了用于校准集成电路的诸如高通滤波器的RC电路的校准电路和方法。 校准电路包括具有可调谐滤波器的滤波器装置，用于对具有预定频率的输入信号进行滤波。 滤波器包括可调谐电阻器元件，饱和检测器，用于通过将比较电压与滤波的输入信号的信号电压进行比较来检测可调谐滤波器的饱和度和不饱和度，校准控制逻辑用于提供递增和递减计数器信号。 校准电路将比较电压设置为第一阈值电压，迭代地向滤波器提供递增计数器信号，直到检测到饱和为止，在检测到饱和后将比较电压降低到预定的第二阈值电压，第二阈值电压比 第一阈值电压，并将递减的计数器信号提供给滤波器，直到检测到不饱和。
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公开(公告)号：US20160109559A1
公开(公告)日：2016-04-21
申请号：US14660471
申请日：2015-03-17
IPC分类号： G01S7/40
CPC分类号： G01S7/4056 , G01S13/34 , G01S13/931 , G01S2007/4073
摘要： An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
摘要翻译： 用于雷达装置的集成电路包括至少一个发射器和至少一个接收器。 集成电路包括：配置为输出控制信号的直接数字合成器DDS; 以及被配置为从DDS接收本地振荡器输入信号和另外的输入信号的乘法器。 在第一操作模式中，DDS和乘法器协作以产生要从雷达设备发射的至少一个发射机信号; 并且在第二操作模式中，DDS和乘法器协作以产生至少一个低频调制的发射机信号，以在内部路由到至少一个接收机，用于校准至少一个接收机。
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4.发明申请INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD FOR FREQUENCY DETECTION 有权集成电路设备，电子设备和频率检测方法公开(公告)号：US20130331050A1
公开(公告)日：2013-12-12
申请号：US13985990
申请日：2011-03-01
IPC分类号： H04B1/06
CPC分类号： H04B1/06 , H04L25/0262
摘要： An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.
摘要翻译： 集成电路包括频率检测器。 频率检测器包括可操作地耦合到定时器并被布置成接收输入载波信号的定时器状态机单元; 确定进入的载波信号是否包括有效频率; 当进入的载波信号被确定为具有有效频率时，生成有效载波指示; 并且响应于该确定，在至少第一定时操作模式和频率检测器的第二定时操作模式之间调整定时器。
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5.发明申请CIRCUITRY FOR AND METHOD OF GENERATING A FREQUENCY MODULATED RADAR TRANSMITTER SIGNAL, A RADAR TRANSCEIVER CIRCUIT AND A RADAR SYSTEM 有权辐射频率调制雷达发射机信号的电路和方法，雷达收发器电路和雷达系统公开(公告)号：US20150219753A1
公开(公告)日：2015-08-06
申请号：US14324322
申请日：2014-07-07
申请人： DIDIER SALLE , OLIVIER DOARE , CHRISTOPHE LANDEZ
发明人： DIDIER SALLE , OLIVIER DOARE , CHRISTOPHE LANDEZ
CPC分类号： G01S7/4008 , G01S7/032 , G01S13/02 , G01S13/343 , G01S13/584 , G01S13/931 , H03C3/0925
摘要： A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.
摘要翻译： 提供了一种生成调频雷达发射机信号的电路和方法。 电路包括调制信号发生器，用于产生具有描述调频雷达发射机信号的所需频率调制的波形的调制信号，并包括用于根据调制信号产生调频雷达发射机信号的PLL电路。 在PLL电路中，可控分频器根据调制信号来控制PLL电路的输出频率。 PLL电路还包括相位检测器，可控振荡器和可能的低通滤波器。 PLL电路还包括被配置为控制相位检测器和可控振荡器中的至少一个的参数以保持PLL电路的环路增益的校准电路。
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公开(公告)号：US09197394B2
公开(公告)日：2015-11-24
申请号：US14402893
申请日：2012-05-29
申请人： Olivier Doare , Christophe Landez
发明人： Olivier Doare , Christophe Landez
CPC分类号： H04L7/0008 , G06F13/4291 , H04L7/04
摘要： Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
摘要翻译： 集成电路的多功能性和灵活性可以通过串行接口（如SPI）的远程控制来实现。 可以通过主节点根据SPI协议实现对SPI从节点的读/写访问。 此外，与从节点SPI相关联的状态机需要本地时钟来执行写访问之后的模拟功能的控制。 串行协议定义串行数据字传输以包括未分配用于传送数据字的数据位值的多个保留时钟周期。 从设备包括耦合到串行时钟线的时钟单元，用于基于保留的时钟周期提供导出的时钟。 派生时钟在从设备内部使用，以执行内部同步操作。
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公开(公告)号：US20150163046A1
公开(公告)日：2015-06-11
申请号：US14402893
申请日：2012-05-29
申请人： Olivier Doare , Christophe Landez
发明人： Olivier Doare , Christophe Landez
CPC分类号： H04L7/0008 , G06F13/4291 , H04L7/04
摘要： Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
摘要翻译： 集成电路的多功能性和灵活性可以通过串行接口（如SPI）的远程控制来实现。 可以通过主节点根据SPI协议实现对SPI从节点的读/写访问。 此外，与从节点SPI相关联的状态机需要本地时钟来执行写访问之后的模拟功能的控制。 串行协议定义串行数据字传输以包括未分配用于传送数据字的数据位值的多个保留时钟周期。 从设备包括耦合到串行时钟线的时钟单元，用于基于保留的时钟周期提供导出的时钟。 派生时钟在从设备内部使用，以执行内部同步操作。
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8.发明申请INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE 有权包含用于控制频率源的频率发生电路的集成电路公开(公告)号：US20110298506A1
公开(公告)日：2011-12-08
申请号：US13145125
申请日：2010-02-10
申请人： Didier Salle , Olivier Doare , Stephane Dugalleix
发明人： Didier Salle , Olivier Doare , Stephane Dugalleix
IPC分类号： H03L7/08
CPC分类号： G01S7/35 , G01S7/032 , G01S13/34 , G01S13/931 , G01S2013/9325 , H03C3/0925 , H03L7/1976
摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for use in an automotive radar system. The frequency generation circuitry comprises low-path modulation circuitry arranged to generate a first, low-path control signal for providing lower frequency modulation of the frequency source, the low-path modulation circuitry comprising a Phase Locked Loop (PLL) arranged to generate the low-path control signal for controlling the frequency source and a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control module operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of at least a first, lower frequency pattern control signal. The frequency generation circuitry further comprises high-path modulation circuitry arranged to generate a second, high-path control signal for providing higher frequency modulation of the frequency source.
摘要翻译： 集成电路包括用于控制在汽车雷达系统中使用的频率源的频率产生电路。 频率产生电路包括低通道调制电路，其被布置为产生用于提供频率源的较低频率调制的第一低路径控制信号，该低通道调制电路包括被配置为产生低电平的锁相环（PLL） 用于控制频率源的PATH控制信号和位于PLL的反馈环路内的分数N分频器，以及频率模式控制模块，其可操作地耦合到分数N分频器，并被布置成通过以下方式控制分数N分频器 至少第一低频模式控制信号。 频率产生电路还包括被设置为产生用于提供频率源的更高频率调制的第二高路径控制信号的高路径调制电路。
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公开(公告)号：US10250213B2
公开(公告)日：2019-04-02
申请号：US15022239
申请日：2013-09-27
摘要： A calibration circuit and a method for calibrating a RC circuit, such as a high-pass filter, of an integrated circuit are provided. The calibration circuit comprises a filter arrangement having tuneable filter for filtering an input signal having a predetermined frequency. The filter comprises tuneable resistor elements, a saturation detector for detecting saturation and non-saturation of the tuneable filter by comparing a comparison voltage with the signal voltage of the filtered input signal, calibration control logic for providing incrementing and decrementing counter signals. The calibration circuit sets the comparison voltage to a first threshold voltage provides iteratively the incrementing counter signal to the filter until saturation is detected reduces the comparison voltage to a predetermined second threshold voltage after saturation is detected, the second threshold voltage being a lower value than the first threshold voltage, and provides the decrementing counter signal to the filter until non-saturation is detected.
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公开(公告)号：US09835715B2
公开(公告)日：2017-12-05
申请号：US14660471
申请日：2015-03-17
CPC分类号： G01S7/4056 , G01S13/34 , G01S13/931 , G01S2007/4073
摘要： An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
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