公开(公告)号：US07661010B2

公开(公告)日：2010-02-09

申请号：US11536709

申请日：2006-09-29

申请人： Jody DeFazio ,  Oswald Becca ,  Peter Nyasulu

发明人： Jody DeFazio ,  Oswald Becca ,  Peter Nyasulu

IPC分类号： G06F1/00

CPC分类号： G11C7/22 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/41 ,  G11C2029/5602

摘要： A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

摘要翻译： 将延迟锁定环（DLL）添加到系统中，以便将写入数据眼中的驱动时钟的精确的PVT不敏感转换提供给系统。 将主从DLL添加到系统中，可以将回波时钟的精确PVT不敏感转换转换为读数据眼。 固化与I / O缓冲器直接接口的时序关键驱动器和接收逻辑可以减少引脚对引脚的偏移。 在固化驱动器和接收逻辑块中利用DLL的时钟相位输出进一步减少了时钟和相关数据信号之间的偏差，并且还消除了对差分时钟的依赖。 该系统允许在时钟占空比上更加宽松的约束。 固化驱动器和接收逻辑块内的电路设计允许简单的逻辑建模，以适应ASIC流程。 固化驱动器和接收逻辑块的物理设计允许在ASIC位置和路由流中简单的配合，以增加实现的便利性和易于重用。

公开(公告)号：US20070283182A1

公开(公告)日：2007-12-06

申请号：US11536709

申请日：2006-09-29

申请人： Jody DEFAZIO ,  Oswald BECCA ,  Peter NYASULU

发明人： Jody DEFAZIO ,  Oswald BECCA ,  Peter NYASULU

IPC分类号： G06F1/00

CPC分类号： G11C7/22 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/41 ,  G11C2029/5602

摘要： A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

摘要翻译： 将延迟锁定环（DLL）添加到系统中，以便将写入数据眼中的驱动时钟的精确的PVT不敏感转换提供给系统。 将主从DLL添加到系统中，可以将回波时钟的精确PVT不敏感转换转换为读数据眼。 固化与I / O缓冲器直接接口的时序关键驱动器和接收逻辑可以减少引脚对引脚的偏移。 在固化驱动器和接收逻辑块中利用DLL的时钟相位输出进一步减少了时钟和相关数据信号之间的偏差，并且还消除了对差分时钟的依赖。 该系统允许在时钟占空比上更加宽松的约束。 固化驱动器和接收逻辑块内的电路设计允许简单的逻辑建模，以适应ASIC流程。 固化驱动器和接收逻辑块的物理设计允许在ASIC位置和路由流中简单的配合，以增加实施的便利性和易于重用。

公开(公告)号：US08296598B2

公开(公告)日：2012-10-23

申请号：US13113550

申请日：2011-05-23

申请人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

发明人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC分类号： G06F1/12 ,  H03L7/00

CPC分类号： G06F5/08

摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

摘要翻译： 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

公开(公告)号：US20110228626A1

公开(公告)日：2011-09-22

申请号：US13113550

申请日：2011-05-23

申请人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

发明人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC分类号： G11C8/00 ,  H03L7/00

CPC分类号： G06F5/08

摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

摘要翻译： 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

公开(公告)号：US07062601B2

公开(公告)日：2006-06-13

申请号：US10430378

申请日：2003-05-07

申请人： Oswald Becca ,  Alan Roth ,  Robert McKenzie

发明人： Oswald Becca ,  Alan Roth ,  Robert McKenzie

IPC分类号： G06F12/00

CPC分类号： G06F17/30982 ,  G06F13/18 ,  G06F13/4247 ,  G11C15/00

摘要： A cam system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMS in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for co-ordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimising the number of CAMs being connected to a common forwarding bus.

摘要翻译： 一种凸轮系统，包括以串联级联装置连接的多个CAM装置，级联中的CAMS通过相应的转发总线连接到相邻的CAM，其中级联中的至多第一CAM连接到来自 主机控制器和至多最后的CAM设备被耦合以将结果转发回主机控制器; 以及发送信号发生装置，用于向最后一个CAM提供SEND信号; 用于协调将搜索结果从最后一个CAM传送到主机控制器的SEND信号，串行级联布置使得连接到公共转发总线的CAM的数量最小化。

公开(公告)号：US07010713B2

公开(公告)日：2006-03-07

申请号：US10352372

申请日：2003-01-27

申请人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

发明人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC分类号： G06F1/12 ,  G06F1/06

CPC分类号： G06F5/08

摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

公开(公告)号：US08209562B2

公开(公告)日：2012-06-26

申请号：US12684026

申请日：2010-01-07

申请人： Jody Defazio ,  Oswald Becca ,  Peter Nyasulu

发明人： Jody Defazio ,  Oswald Becca ,  Peter Nyasulu

IPC分类号： G06F1/12 ,  G06F1/04

CPC分类号： G11C7/22 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/41 ,  G11C2029/5602

摘要： In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

摘要翻译： 在存储器接口中，将延迟锁定环（DLL）添加到系统中，以便将驱动时钟的精确的PVT不敏感转换提供给写入数据眼睛。 将主从DLL添加到系统中，可以将回波时钟的精确PVT不敏感转换转换为读数据眼。 固化与I / O缓冲器直接接口的时序关键驱动器和接收逻辑可以减少引脚对引脚的偏移。 在固化驱动器和接收逻辑块中利用DLL的时钟相位输出进一步减少了时钟和相关数据信号之间的偏差，并且还消除了对差分时钟的依赖。 该系统允许在时钟占空比上更加宽松的约束。 固化驱动器和接收逻辑块内的电路设计允许简单的逻辑建模，以适应ASIC流程。 固化驱动器和接收逻辑块的物理设计允许在ASIC位置和路由流中简单的配合，以增加实现的便利性和易于重用。

公开(公告)号：US20100122104A1

公开(公告)日：2010-05-13

申请号：US12684026

申请日：2010-01-07

申请人： Jody DEFAZIO ,  Oswald BECCA ,  Peter NYASULU

发明人： Jody DEFAZIO ,  Oswald BECCA ,  Peter NYASULU

IPC分类号： G06F1/12 ,  G06F1/06 ,  G06F1/10

CPC分类号： G11C7/22 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/41 ,  G11C2029/5602

摘要： In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

摘要翻译： 在存储器接口中，将延迟锁定环（DLL）添加到系统中，以便将驱动时钟的精确的PVT不敏感转换提供给写入数据眼睛。 将主从DLL添加到系统中，可以将回波时钟的精确PVT不敏感转换转换为读数据眼。 固化与I / O缓冲器直接接口的时序关键驱动器和接收逻辑可以减少引脚对引脚的偏移。 在固化驱动器和接收逻辑块中利用DLL的时钟相位输出进一步减少了时钟和相关数据信号之间的偏差，并且还消除了对差分时钟的依赖。 该系统允许在时钟占空比上更加宽松的约束。 固化驱动器和接收逻辑块内的电路设计允许简单的逻辑建模，以适应ASIC流程。 固化驱动器和接收逻辑块的物理设计允许在ASIC位置和路由流中简单的配合，以增加实现的便利性和易于重用。

公开(公告)号：US20100033216A1

公开(公告)日：2010-02-11

申请号：US12543839

申请日：2009-08-19

申请人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

发明人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC分类号： H03L7/00

CPC分类号： G06F5/08

摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

摘要翻译： 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

公开(公告)号：US07558909B2

公开(公告)日：2009-07-07

申请号：US11548766

申请日：2006-10-12

申请人： Alan Roth ,  Robert McKenzie ,  Oswald Becca

发明人： Alan Roth ,  Robert McKenzie ,  Oswald Becca

IPC分类号： G06F12/00

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

摘要翻译： 公开了一种用于搜索和删除CAM阵列中的分段宽字条目的系统和方法。 执行正常的CAM搜索操作以找到宽字的第一字段。 一旦找到，执行搜索和删除操作，以沿着第一CAM阵列方向找到宽字的所有连续字段，其中最后一个字段被标记为删除的字段。 一旦最后一个字段被删除，宽字被认为已被删除，因为后续搜索宽字不会找到其最后一个字段。 然后沿着相反的CAM阵列方向执行清除操作，以删除所删除的宽字的所有字段。 CAM阵列的每一行中的匹配处理电路可以将搜索结果传递到其上方或下方的相邻行，以确保在搜索和删除操作中仅找到属于宽字的字段，并在清除操作中删除。