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公开(公告)号：US20100033216A1
公开(公告)日：2010-02-11
申请号：US12543839
申请日：2009-08-19
Applicant: Alan Roth , Oswald Becca , Pedro Ovalle
Inventor： Alan Roth , Oswald Becca , Pedro Ovalle
IPC: H03L7/00
CPC classification number: G06F5/08
Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。
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公开(公告)号：US20060103439A1
公开(公告)日：2006-05-18
申请号：US11305433
申请日：2005-12-14
Applicant: Alan Roth , Oswald Becca , Pedro Ovalle
Inventor： Alan Roth , Oswald Becca , Pedro Ovalle
IPC: H03L7/06
CPC classification number: G06F5/08
Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
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3.发明授权Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal 有权用于静态RAM器件的双数据速率输出锁存器具有边沿触发触发器以输出DDR信号以与第二时钟信号同步公开(公告)号：US08069363B2
公开(公告)日：2011-11-29
申请号：US12543839
申请日：2009-08-19
Applicant: Alan Roth , Oswald Becca , Pedro Ovalle
Inventor： Alan Roth , Oswald Becca , Pedro Ovalle
CPC classification number: G06F5/08
Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并且输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。
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Patent Agency Ranking
公开(公告)号：US07596710B2
公开(公告)日：2009-09-29
申请号：US11305433
申请日：2005-12-14
Applicant: Alan Roth , Oswald Becca , Pedro Ovalle
Inventor： Alan Roth , Oswald Becca , Pedro Ovalle
CPC classification number: G06F5/08
Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。
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公开(公告)号：US08296598B2
公开(公告)日：2012-10-23
申请号：US13113550
申请日：2011-05-23
Applicant: Alan Roth , Oswald Becca , Pedro Ovalle
Inventor： Alan Roth , Oswald Becca , Pedro Ovalle
CPC classification number: G06F5/08
Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。
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公开(公告)号：US20110228626A1
公开(公告)日：2011-09-22
申请号：US13113550
申请日：2011-05-23
Applicant: Alan Roth , Oswald Becca , Pedro Ovalle
Inventor： Alan Roth , Oswald Becca , Pedro Ovalle
CPC classification number: G06F5/08
Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。
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公开(公告)号：US07010713B2
公开(公告)日：2006-03-07
申请号：US10352372
申请日：2003-01-27
Applicant: Alan Roth , Oswald Becca , Pedro Ovalle
Inventor： Alan Roth , Oswald Becca , Pedro Ovalle
CPC classification number: G06F5/08
Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
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公开(公告)号：US06313664B1
公开(公告)日：2001-11-06
申请号：US09528857
申请日：2000-03-20
Applicant: Geoffrey B. Hall , Pedro Ovalle , Dzung T. Tran
Inventor： Geoffrey B. Hall , Pedro Ovalle , Dzung T. Tran
IPC: H03K190185
CPC classification number: H03K19/00361 , H03K17/167 , H03K19/00384
Abstract: A primary driver is activated to drive an output signal in response to an input signal. A reference signal is generated in response to the input signal. The output signal is compared to the reference signal. When the output signal lags the reference signal by a predefined amount an auxiliary driver is activated.
Abstract translation: 主驱动器被激活以响应于输入信号来驱动输出信号。 响应于输入信号产生参考信号。 将输出信号与参考信号进行比较。 当输出信号以预定量滞后参考信号时，辅助驱动器被激活。
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