Abstract:
A display device is provided, including a panel having a plurality of display cells, wherein the display cells are respectively connected to a plurality of data lines and gate lines. A plurality of source driver chips output a plurality of pixel signals to the data lines, wherein each source driver chip comprises a timing controller integrated therein for receiving an image control signal provided by a host and generating a plurality of timing control signals and the pixel signals according to-the image control signal. A gate driver chip outputs corresponding scan signals to the gate lines. A printed circuit board is also provided, and a plurality of transmission lines are routed on the printed circuit board and connected the source driver chips.
Abstract:
A data driver including a receiver, a skew adjusting circuit and a processing device is provided. The receiver samples image data on a data bus according to a processed pixel clock signal. The image data includes pixel data during active periods and a test pattern repeatedly inserted in the image data during blanking periods. The skew adjusting circuit receives a pixel clock signal and adjusts a clock phase of the pixel clock signal by delaying the pixel clock signal with a controllable skew according to a feedback control signal so as to generate the processed pixel clock signal. The processing device stores a predetermined test pattern synchronized with the inserted test pattern, determines an optimum skew by comparing the sampled test patterns with the predetermined test pattern, and generates the feedback control signal including information indicating the optimum skew.
Abstract:
A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.
Abstract:
An apparatus for driving a display panel is provided. The apparatus is adapted to a LCD panel. The apparatus at least has a processor, a first and second timing controllers and a first and second group of source drivers. Real pixels are input from an input port of the processor. The real pixels are converted to impulsive pixels with a pre-determined frame rate. The impulsive pixels are divided into two groups of pixels by the processor. The two groups of pixels are simultaneously sent to the source drivers though two timing controllers, respectively. Finally, the source drivers generate driving voltages for the display panel.
Abstract:
A data driver including a receiver, a skew adjusting circuit and a processing device is provided. The receiver samples image data on a data bus according to a processed pixel clock signal. The image data includes pixel data during active periods and a test pattern repeatedly inserted in the image data during blanking periods. The skew adjusting circuit receives a pixel clock signal and adjusts a clock phase of the pixel clock signal by delaying the pixel clock signal with a controllable skew according to a feedback control signal so as to generate the processed pixel clock signal. The processing device stores a predetermined test pattern synchronized with the inserted test pattern, determines an optimum skew by comparing the sampled test patterns with the predetermined test pattern, and generates the feedback control signal including information indicating the optimum skew.
Abstract:
An interface circuit for data transmission and the method thereof is described. The interface circuit includes a transmitter providing data through first data signals during the data periods corresponding to rising and falling edges of a clock signal, a transition detection unit selectively asserting a detection signal in response to the number of the first data signals having transitions between every two adjacent data periods, a transition reduction unit generating second data signals by outputting the inverted and non-inverted first data signals respectively when the detection signal is asserted and de-asserted, and a receiver restoring the data from the second data signals and the detection signal.
Abstract:
A method for transmitting image data to a driver of a display is provided, in which the image data include pixel values each represented by a number of bits. The method includes the steps of sequentially transmitting at least two bits of one of the pixel values during a first period through a data line; and sequentially transmitting at least two bits of another one of the pixel values during a second period next to the first period through the data line, in which an order of the last bit transmitted during the first period is the same as that of the first bit transmitted during the second period.
Abstract:
An overdrive gray level data modifier and method of looking up thereof are provided. The overdrive data modifier obtains and outputs overdrive gray level data according to several overdrive gray values corresponding to several previous gray level index values and several current gray level index values. The overdrive data modifier includes a first, a second, a third and a fourth memory unit. The overdrive gray values are respectively stored in the first, the second, the third and the fourth memory unit. Firstly, a previous gray level index value and a current gray level index value are compared according to a current frame gray level data and a previous frame gray level data, and at least a corresponding overdrive gray level data are obtained from the overdrive gray value. At last, the overdrive gray level data are obtained according to the corresponding overdrive gray level data.
Abstract:
A method for transmitting image data to a driver of a display is provided, in which the image data include pixel values each represented by a number of bits. The method includes the steps of sequentially transmitting at least two bits of one of the pixel values during a first period through a data line; and sequentially transmitting at least two bits of another one of the pixel values during a second period next to the first period through the data line, in which an order of the last bit transmitted during the first period is the same as that of the first bit transmitted during the second period.
Abstract:
A display device is provided, including a panel, source driver chips, a gate driver chip, a printed circuit board and transmission lines. The panel includes light emitting elements and display cells. The display cells are respectively connected to data lines and gate lines. The source driver chips output pixel signals to the data lines. At least one source driver chip includes a timing controller integrated therein for generating timing control signals and the pixel signals according to an image control signal provided by a host. The gate driver chip outputs corresponding scan signals to the gate lines. The transmission lines are routed on the printed circuit board and connect to the source driver chips.