公开(公告)号：US07571410B2

公开(公告)日：2009-08-04

申请号：US11740479

申请日：2007-04-26

Applicant: Phillip J. Restle

Inventor： Phillip J. Restle

IPC: G06F17/50

CPC classification number: G06F1/10

Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

Abstract translation: 用于在集成电路中分配时钟信号的集成电路（IC），IC组件和电路包括其中具有至少一个导体的电容时钟分配电路。 在集成电路的金属层中形成至少一个电感器，并且耦合到时钟分配电路。 通常以分布在整个集成电路中的多个螺旋电感器的形式的电感器提供选择为在谐振时与电容时钟分配电路谐振的电感值，降低功率消耗，同时可以提高歪斜和抖动性能。

公开(公告)号：US20080198700A1

公开(公告)日：2008-08-21

申请号：US12045059

申请日：2008-03-10

Applicant: Robert L. Franch ,  William V. Huott ,  Norman K. James ,  Phillip J. Restle ,  Timothy M. Skergan

Inventor： Robert L. Franch ,  William V. Huott ,  Norman K. James ,  Phillip J. Restle ,  Timothy M. Skergan

IPC: G04F10/00

CPC classification number: G01R31/31725 ,  G01R31/318594

Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

Abstract translation: 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。

公开(公告)号：US5610528A

公开(公告)日：1997-03-11

申请号：US496236

申请日：1995-06-28

Applicant: James S. Neely ,  Phillip J. Restle

Inventor： James S. Neely ,  Phillip J. Restle

IPC: G01B7/30 ,  G01B21/22 ,  G01D5/241 ,  G01R27/26 ,  H01G5/14

CPC classification number: A61B5/1071 ,  A61B5/4528 ,  G01D5/2412 ,  A61B5/6804 ,  A61B5/6806

Abstract: A capacitive bend sensor includes a first element having a comb-patterned portion of conducting material, and a second element having a comb-patterned portion of conducting material. A dielectric material is disposed between the comb-patterned portion of the first element and the comb-patterned portion of the second element. The first element is bonded to the second element such that the comb-patterned portion of the first element slides relative to the comb-patterned portion of the second element when the first and second elements are bent. Bend angle is measured according to the alignment of the comb-patterned portion of the first element and the comb-patterned portion of the second element. The sensor may be coupled to a human finger to measure bend angle of the finger, or may be coupled to a joint of a human body to measure bend angle of the joint.

Abstract translation: 电容弯曲传感器包括具有导电材料的梳形图案部分的第一元件和具有导电材料的梳形图案部分的第二元件。 电介质材料设置在第一元件的梳形图案部分和第二元件的梳形图案部分之间。 当第一和第二元件弯曲时，第一元件被结合到第二元件，使得第一元件的梳形图案部分相对于第二元件的梳状图案部分滑动。 根据第一元件的梳形图案部分和第二元件的梳形图案部分的对准来测量弯曲角度。 传感器可以联接到人的手指以测量手指的弯曲角度，或者可以耦合到人体的关节以测量关节的弯曲角度。

公开(公告)号：US08516426B2

公开(公告)日：2013-08-20

申请号：US13217429

申请日：2011-08-25

Applicant: Pradip Bose ,  Gary D. Carpenter ,  Michael S. Floyd ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

Inventor： Pradip Bose ,  Gary D. Carpenter ,  Michael S. Floyd ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

IPC: G06F17/50 ,  G06F9/455 ,  G06F11/22

CPC classification number: H01L23/50 ,  G06F17/5045 ,  G06F2217/78 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

Abstract: A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.

Abstract translation: 提供了一种用于管理具有两个或更多个层，多个垂直功率传递结构和多个堆叠组件的三维芯片堆叠上的功率分配的方法。 至少两个堆叠组件位于不同的层。 存储分别具有不同功耗的工作模式。 基于针对其的各个操作模式确定所述至少两个堆叠组件中的每一个的相应的有效功率预算，以及包括或排除所述至少两个堆叠的至少一些堆叠组件的功率特性和热特性 组件。 基于用于至少两个堆叠组件中的每一个，功率约束和热约束的相应的有效功率预算来选择性地接受或重新分配针对至少两个堆叠组件的多个操作模式中的各个操作模式。 功率约束包括垂直结构电气约束。

公开(公告)号：US07961559B2

公开(公告)日：2011-06-14

申请号：US12539635

申请日：2009-08-12

Applicant: Robert C. Dixon ,  Robert L. Franch ,  Phillip J. Restle

Inventor： Robert C. Dixon ,  Robert L. Franch ,  Phillip J. Restle

IPC: G04F8/00 ,  H03K3/017 ,  H03H11/26

CPC classification number: G01R31/31725 ,  G01R31/318594

Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

Abstract translation: 用于测量片上全局时钟的占空比不确定性的电路和方法。 全局时钟提供给本地时钟缓冲器的延迟线。 延迟线抽头（变频器输出）是由本地时钟缓冲器计时的寄存器的输入。 寄存器捕获时钟边沿，这些边沿被过滤以识别每个边缘的单个位置。 边缘之间的空间不平衡表明占空比不平衡。 上/下信号由任何不平衡产生，并传递到锁相环以调整平衡。

公开(公告)号：US20130055185A1

公开(公告)日：2013-02-28

申请号：US13217429

申请日：2011-08-25

Applicant: PRADIP BOSE ,  GARY D. CARPENTER ,  MICHAEL S. FLOYD ,  EREN KURSUN ,  PHILLIP J. RESTLE ,  MICHAEL R. SCHEUERMANN

Inventor： PRADIP BOSE ,  GARY D. CARPENTER ,  MICHAEL S. FLOYD ,  EREN KURSUN ,  PHILLIP J. RESTLE ,  MICHAEL R. SCHEUERMANN

IPC: G06F17/50

CPC classification number: H01L23/50 ,  G06F17/5045 ,  G06F2217/78 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

Abstract: A method is provided for managing power distribution on a 3D chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.

Abstract translation: 提供了一种用于管理具有两个或更多个层，多个垂直功率传递结构和多个堆栈组件的3D芯片堆叠上的功率分配的方法。 至少两个堆叠组件位于不同的层。 存储分别具有不同功耗的工作模式。 基于针对其的各个操作模式确定所述至少两个堆叠组件中的每一个的相应的有效功率预算，以及包括或排除所述至少两个堆叠的至少一些堆叠组件的功率特性和热特性 组件。 基于用于至少两个堆叠组件中的每一个，功率约束和热约束的相应的有效功率预算来选择性地接受或重新分配针对至少两个堆叠组件的多个操作模式中的各个操作模式。 功率约束包括垂直结构电气约束。

公开(公告)号：US20090295449A1

公开(公告)日：2009-12-03

申请号：US12539635

申请日：2009-08-12

Applicant: Robert C. Dixon ,  Robert L. Franch ,  Phillip J. Restle

Inventor： Robert C. Dixon ,  Robert L. Franch ,  Phillip J. Restle

IPC: H03H11/26

CPC classification number: G01R31/31725 ,  G01R31/318594

Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

Abstract translation: 用于测量片上全局时钟的占空比不确定性的电路和方法。 全局时钟提供给本地时钟缓冲器的延迟线。 延迟线抽头（变频器输出）是由本地时钟缓冲器计时的寄存器的输入。 寄存器捕获时钟边沿，这些边沿被过滤以识别每个边缘的单个位置。 边缘之间的空间不平衡表明占空比不平衡。 上/下信号由任何不平衡产生，并传递到锁相环以调整平衡。

公开(公告)号：US07456671B2

公开(公告)日：2008-11-25

申请号：US11622004

申请日：2007-01-11

Applicant: Charlie C. Hwang ,  Phillip J. Restle ,  Leon J. Sigal

Inventor： Charlie C. Hwang ,  Phillip J. Restle ,  Leon J. Sigal

IPC: H03H11/26

CPC classification number: H03H11/26

Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.

Abstract translation: 描述了可以实现几乎无限的精细分辨率和无限延迟范围的分层和模块化的时钟可编程延迟电路结构。 相同的电路也可以应用于需要在定时应用中进行微调的关键电路。 模块化设计允许电路及其布局由软件合成，以实现所需的延迟分辨率和范围。 内部节点的恒定容性负载通过数字控制增强实现延迟的线性度。

公开(公告)号：US07237217B2

公开(公告)日：2007-06-26

申请号：US10720564

申请日：2003-11-24

Applicant: Phillip J. Restle

Inventor： Phillip J. Restle

IPC: G06F17/50

CPC classification number: G06F1/10

Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

Abstract translation: 用于在集成电路中分配时钟信号的集成电路（IC），IC组件和电路包括其中具有至少一个导体的电容时钟分配电路。 在集成电路的金属层中形成至少一个电感器，并且耦合到时钟分配电路。 通常以分布在整个集成电路中的多个螺旋电感器的形式的电感器提供选择为在谐振时与电容时钟分配电路谐振的电感值，降低功率消耗，同时可以提高歪斜和抖动性能。

公开(公告)号：US06531759B2

公开(公告)日：2003-03-11

申请号：US09777540

申请日：2001-02-06

Applicant: Richard A. Wachnik ,  Henry A. Nye, III ,  Charles R. Davis ,  Theodore H. Zabel ,  Phillip J. Restle

Inventor： Richard A. Wachnik ,  Henry A. Nye, III ,  Charles R. Davis ,  Theodore H. Zabel ,  Phillip J. Restle

IPC: H01L23552

CPC classification number: H01L23/556 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025

Abstract: An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.