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1.发明申请DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE 审中-公开用于测量和维护平衡时间周期的占空比测量电路公开(公告)号：US20080198700A1
公开(公告)日：2008-08-21
申请号：US12045059
申请日：2008-03-10
IPC分类号： G04F10/00
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译： 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。
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2.发明申请METHOD FOR BUILT IN SELF TEST FOR MEASURING TOTAL TIMING UNCERTAINTY IN A DIGITAL DATA PATH 审中-公开用于在数字数据路径中测量总时间不确定度的自检中的方法公开(公告)号：US20080198699A1
公开(公告)日：2008-08-21
申请号：US12045053
申请日：2008-03-10
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译： 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）被输入到在进展由互补时钟对时钟控制通过延迟线来捕获发射时钟的进展和确定任何变型的寄存器（例如，从抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。
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3.发明授权Built in self test circuit for measuring total timing uncertainty in a digital data path 有权内置自检电路，用于测量数字数据路径中的总时序不确定度公开(公告)号：US07400555B2
公开(公告)日：2008-07-15
申请号：US10712925
申请日：2003-11-13
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译： 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。
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4.发明申请DUTY CYCLE MEASUREMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE 有权用于测量和维护平衡时间周期的占空比测量电路公开(公告)号：US20090295449A1
公开(公告)日：2009-12-03
申请号：US12539635
申请日：2009-08-12
IPC分类号： H03H11/26
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
摘要翻译： 用于测量片上全局时钟的占空比不确定性的电路和方法。 全局时钟提供给本地时钟缓冲器的延迟线。 延迟线抽头（变频器输出）是由本地时钟缓冲器计时的寄存器的输入。 寄存器捕获时钟边沿，这些边沿被过滤以识别每个边缘的单个位置。 边缘之间的空间不平衡表明占空比不平衡。 上/下信号由任何不平衡产生，并传递到锁相环以调整平衡。
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5.发明授权Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle 有权用于测量和维持平衡时钟占空比的占空比测量电路公开(公告)号：US07961559B2
公开(公告)日：2011-06-14
申请号：US12539635
申请日：2009-08-12
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
摘要翻译： 用于测量片上全局时钟的占空比不确定性的电路和方法。 全局时钟提供给本地时钟缓冲器的延迟线。 延迟线抽头（变频器输出）是由本地时钟缓冲器计时的寄存器的输入。 寄存器捕获时钟边沿，这些边沿被过滤以识别每个边缘的单个位置。 边缘之间的空间不平衡表明占空比不平衡。 上/下信号由任何不平衡产生，并传递到锁相环以调整平衡。
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公开(公告)号：US07944229B2
公开(公告)日：2011-05-17
申请号：US12543215
申请日：2009-08-18
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
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公开(公告)号：US5212616A
公开(公告)日：1993-05-18
申请号：US781446
申请日：1991-10-23
申请人： Sang H. Dhong , Robert L. Franch
发明人： Sang H. Dhong , Robert L. Franch
IPC分类号： G05F1/56 , H01L27/08 , H01L27/092 , H03K19/00
CPC分类号： H01L27/0921
摘要： An improved latch-up protection circuit is disclosed which prevents damage to a CMOS integrated circuit chip due to transient surges or internal-circuitry initiated latch-ups and which clears any latch-up condition or SCR mode. In each embodiment, the latch-up protection circuit is integrated with an on-chip voltage regulation circuit which provides on-chip power to the internal chip circuitry. A first approach to implementing the latch-up protection circuit is to detect an average current through the power transistor of the voltage regulation circuit over a few microseconds. Should the average current exceed a preset value, then the power transistor is turned off and the power (V.sub.DDI) supplied to the internal chip circuitry is reduced to zero, thereby removing the latch-up condition. In a second approach, the on-chip voltage (V.sub.DDI) supplied to internal chip circuitry is compared with a reference voltage signal representative of the occurrence of a latch-up condition, i.e., with the nominal external power supply. When the on-chip power supply voltage V.sub.DDI becomes lower than the trigger voltage, then the power transistor and voltage regulation circuit is disabled, thereby reducing the latch-up condition. Both CMOS and NMOS implementations of the combination voltage regulation and latch-up protection circuit are disclosed.
摘要翻译： 公开了一种改进的闭锁保护电路，其防止由于瞬态浪涌或内部电路启动的闭锁而损坏CMOS集成电路芯片，并且其清除任何闩锁状态或SCR模式。 在每个实施例中，闩锁保护电路与片上电压调节电路集成，片上电压调节电路为内部芯片电路提供片上电源。 实现闩锁保护电路的第一种方法是在几微秒内检测通过电压调节电路的功率晶体管的平均电流。 如果平均电流超过预设值，则功率晶体管关闭，提供给内部芯片电路的功率（VDDI）减小到零，从而消除闩锁状态。 在第二种方法中，将提供给内部芯片电路的片上电压（VDDI）与表示闩锁状态的出现的参考电压信号进行比较，即使用额定外部电源。 当片上电源电压VDDI变得低于触发电压时，功率晶体管和电压调节电路被禁止，从而减少闭锁状态。 公开了组合电压调节和闭锁保护电路的CMOS和NMOS实现。
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公开(公告)号：US07762721B2
公开(公告)日：2010-07-27
申请号：US12061692
申请日：2008-04-03
申请人： Robert L. Franch , Keith A. Jenkins
发明人： Robert L. Franch , Keith A. Jenkins
IPC分类号： G01K7/00
CPC分类号： H01L27/0251 , G01K7/01 , G01K7/015
摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
摘要翻译： 一种器件温度测量电路，包括器件温度测量电路的集成电路（IC），表征器件温度的方法和监测温度的方法。 电路包括恒流源和夹紧装置。 钳位装置选择性地从恒流源分流电流，或允许电流流过PN结，其可以是场效应晶体管（FET）的主体到源极/漏极结。 电压测量直接来自PN结。 结温从测量的结电压确定。
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公开(公告)号：US20080291970A1
公开(公告)日：2008-11-27
申请号：US12177311
申请日：2008-07-22
申请人： Robert L. Franch , Keith A. Jenkins
发明人： Robert L. Franch , Keith A. Jenkins
IPC分类号： G01K7/01
CPC分类号： H01L27/0251 , G01K7/01 , G01K7/015
摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
摘要翻译： 一种器件温度测量电路，包括器件温度测量电路的集成电路（IC），表征器件温度的方法和监测温度的方法。 电路包括恒流源和夹紧装置。 钳位装置选择性地从恒流源分流电流，或允许电流流过PN结，其可以是场效应晶体管（FET）的主体到源极/漏极结。 电压测量直接来自PN结。 结温从测量的结电压确定。
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公开(公告)号：US20080187024A1
公开(公告)日：2008-08-07
申请号：US12061696
申请日：2008-04-03
申请人： Robert L. Franch , Keith A. Jenkins
发明人： Robert L. Franch , Keith A. Jenkins
IPC分类号： G01K7/01
CPC分类号： H01L27/0251 , G01K7/01 , G01K7/015
摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
摘要翻译： 一种器件温度测量电路，包括器件温度测量电路的集成电路（IC），表征器件温度的方法和监测温度的方法。 电路包括恒流源和夹紧装置。 钳位装置选择性地从恒流源分流电流，或允许电流流过PN结，其可以是场效应晶体管（FET）的主体到源极/漏极结。 电压测量直接来自PN结。 结温从测量的结电压确定。
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