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公开(公告)号：US09684019B2
公开(公告)日：2017-06-20
申请号：US13451515
申请日：2012-04-19
IPC分类号： G01R21/133
CPC分类号： G01R21/133
摘要： A wire management method using a wire manager including current sensing features provides input for power measurement and management systems. The wire manager may be a single wire or single bundle retaining device with a current sensor such as a hall effect sensor integrated therein, or may be a multi-wire management housing with multiple current sensing devices disposed inside for measuring the current through multiple wires. The wires may be multiple branch circuits in a power distribution panel or raceway, and the wire manager may be adapted for mounting in such a panel or raceway. Voltage sensing may also be incorporated within the sensors by providing an electrically conductive plate, wire or other element that capacitively couples to the corresponding wire.
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公开(公告)号：US09105627B2
公开(公告)日：2015-08-11
申请号：US13289071
申请日：2011-11-04
IPC分类号： H01F5/00 , H01L27/08 , H01L23/498 , H01L23/522 , H01L23/64 , H01L49/02 , H01F17/00 , H01F41/00
CPC分类号： H01L23/49822 , H01F17/0013 , H01F41/005 , H01F2017/0086 , H01L23/5227 , H01L23/645 , H01L28/10 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/01322 , H01L2924/15311 , H01L2924/30107 , H01L2924/00
摘要： A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.
摘要翻译： 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。
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3.发明申请公开(公告)号：US20080225615A1
公开(公告)日：2008-09-18
申请号：US12128526
申请日：2008-05-28
IPC分类号： G11C29/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译： 用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。 脉冲发生器耦合到待测量的存储单元连接到的位线。 因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。 在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。 或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。 脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。 读取电流是电流之间的差异。
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公开(公告)号：US20080122490A1
公开(公告)日：2008-05-29
申请号：US11563888
申请日：2006-11-28
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译： 在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及 状态捕捉块可操作地连接以接收当前信元信号。 将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号 检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。
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5.发明申请Circuit for Dynamic Circuit Timing Synthesis and Monitoring of Critical Paths and Environmental Conditions of an Integrated Circuit 失效用于动态电路定时的电路综合和监控集成电路的关键路径和环境条件公开(公告)号：US20080104561A1
公开(公告)日：2008-05-01
申请号：US11549138
申请日：2006-10-13
申请人： Gary D. Carpenter , Alan J. Drake , Harmander S. Deogun , Michael S. Floyd , Norman K. James , Robert M. Senger
发明人： Gary D. Carpenter , Alan J. Drake , Harmander S. Deogun , Michael S. Floyd , Norman K. James , Robert M. Senger
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).
摘要翻译： 用于在不同的温度，频率和电压（包括局部噪声和下垂）下动态地监测集成电路的操作以及用于检测早期寿命磨损机制（例如，NBTI，热电子）的电路。
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6.发明授权Ultra high frequency ring oscillator with voltage controlled frequency capabilities 失效具有电压控制频率功能的超高频环形振荡器公开(公告)号：US07113048B2
公开(公告)日：2006-09-26
申请号：US10988463
申请日：2004-11-12
CPC分类号： H03K3/0315 , H03K3/356139 , H03K5/133 , H03L7/0995
摘要： A pseudo Set/Reset latch circuit is configured with modified NOR or NAND gates wherein one of the series pull-up devices or pull-down devices is removed. A minimum of three pseudo Set/Reset latches may be coupled as a ring oscillator generating an output and a non-skewed complementary output. Additionally, feed-forward inverting stages may be coupled in parallel with inverting paths in the ring oscillator primary path to further increase the frequency range of the ring oscillator. The pseudo Set/Reset latch circuits and the feed-forward inverting stages may be configured with voltage controlled devices that alter the delay of the stages as a means for varying the frequency of the ring oscillator either by varying the current drive of the circuitry driving the output of the latch stages or by varying the conductance of devices coupling between the latch stages. Feedforward inverting stages may comprise pseudo latches or inverter gates.
摘要翻译： 伪置位/复位锁存电路配置有修改的NOR或NAND门，其中串联上拉器件或下拉器件中的一个被去除。 可以将至少三个伪设置/复位锁存器耦合作为产生输出和非偏斜互补输出的环形振荡器。 此外，前馈反相级可以与环形振荡器主路径中的反相路径并联耦合，以进一步增加环形振荡器的频率范围。 伪设置/复位锁存电路和前馈反相级可以配置有电压控制的装置，其通过改变驱动电路的电路的电流驱动来改变级的延迟，作为改变环形振荡器的频率的手段 锁存级的输出或通过改变耦合在锁存级之间的器件的电导。 前馈反相级可以包括伪锁存器或反相器门。
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公开(公告)号：US06963629B2
公开(公告)日：2005-11-08
申请号：US09918809
申请日：2001-07-31
CPC分类号： H03L7/107 , H03D13/004 , H03L7/0898
摘要： A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO output and a lag error signal is generated if the reference signal lags the VCO output the lead and lag error may result from a combination for phase and frequency differences between the reference signal and the VCO output. A time window is used to sample the polarity of the lead and lag error signals by incrementing and decrementing a phase error signal. If the phase error signal reaches a threshold value within the time window, a Reset Delta pulse is generated and if the phase error signals does not reach the maximum delta value within the time window a Reset Total pulse is generated. A variable first gain signal is increased on each Reset Delta pulse and decreased on each Reset Total pulse and limited to a value between predetermined maximum and minimum values. The first gain signal is multiplied by a Pump current increment and added to a minimum Pump current to generate a variable Pump current. A variable second gain signal proportional to the time the reference signal leads and lags the VCO signal multiplies the Pump current. The amplified Pump current is summed with an integral of the amplified Pump current to generate a control signal. The control signal is applied to the VCO and determines the frequency of the VCO output.
摘要翻译： 比较参考信号和压控振荡器（VCO）输出的相对相位和频率差。 如果参考信号引导VCO输出，则产生引导误差信号，如果参考信号滞后于VCO输出引起滞后误差信号产生滞后误差，则滞后误差可能由参考信号和 VCO输出。 时间窗口用于通过递增和递减相位误差信号来对引线和滞后误差信号的极性进行采样。 如果相位误差信号在时间窗内达到阈值，则产生复位增量脉冲，如果相位误差信号在时间窗口内未达到最大增量值，则产生复位总脉冲。 在每个复位增量脉冲上增加可变的第一增益信号，并在每个复位总脉冲上减小，并限制在预定的最大和最小值之间的值。 第一个增益信号乘以泵电流增量，并加到最小泵电流以产生可变泵电流。 与参考信号引导和滞后于VCO信号的时间成比例的可变第二增益信号与泵电流相乘。 放大的泵电流与放大的泵电流的积分相加以产生控制信号。 控制信号被施加到VCO并确定VCO输出的频率。
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公开(公告)号：US06753698B2
公开(公告)日：2004-06-22
申请号：US10064708
申请日：2002-08-08
申请人： Gary D. Carpenter , Francis Chan , Kevin J. Nowka , Hongfei Wu
发明人： Gary D. Carpenter , Francis Chan , Kevin J. Nowka , Hongfei Wu
IPC分类号： H03K190175
CPC分类号： H03K19/003 , H03K19/0016
摘要： An I/O driver comprising: a circuit adapted to be powered by a first power supply. The circuit is adapted to receive a first signal referenced to the voltage of a second power supply and is adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply. The circuit is adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.
摘要翻译： 一种I / O驱动器，包括：适于由第一电源供电的电路。 电路适于接收参考第二电源的电压的第一信号，并且适于将第一信号转换成与第一信号相同的逻辑值的第二信号，并参考第一电源的电压。 该电路适于在第二电源断电时将第二信号保持在I / O驱动器的输出上。
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公开(公告)号：US06529082B1
公开(公告)日：2003-03-04
申请号：US09975187
申请日：2001-10-11
IPC分类号： H03L700
CPC分类号： H03L7/0896 , H03L7/0898 , H03L7/107
摘要： A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal. A first bi-directional transfer gate is coupled between the output nodes of the first and third CSs and is controlled by a Mode control signal and a second bi-directional transfer gate is coupled between the output nodes of the second and fourth CSs and is also controlled by the Mode control signal. States of the control signals allow a dual mode where either a first or second current level may be delivered into or out of components coupled to the first and second charge pump nodes.
摘要翻译： 电荷泵有两个电荷泵节点。 第一电荷泵节点具有源极端子连接到正电源电压的第一电流源（CS）和连接到第一电荷泵节点的输出端子，其中P沟道金属氧化物硅晶体管（PFET）由第一控制 信号。 第一电荷泵节点还连接到具有连接到接地电源电压的源极端子的第二CS，以及通过第二控制信号控制的NFET连接到第二CS的输出端子。 第二电荷泵节点具有连接到正电源电压的源极端子的第三CS和与由第三控制信号控制的PFET连接到第二电荷泵节点的输出端子。 第二电荷泵节点还连接到具有连接到接地电源电压的源极端子的第四CS和连接到具有由第四控制信号控制的NFET的第二CS的输出端子。 第一双向传输门耦合在第一和第三CS的输出节点之间，并且由模式控制信号控制，第二双向传输门耦合在第二和第四CS的输出节点之间，并且也是 由模式控制信号控制。 控制信号的状态允许双模式，其中第一或第二电流电平可以被传送到耦合到第一和第二电荷泵节点的组件中或从耦合到第一和第二电荷泵节点的组件中。
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公开(公告)号：US06515530B1
公开(公告)日：2003-02-04
申请号：US09974985
申请日：2001-10-11
IPC分类号： G06F104
CPC分类号： G06F1/3237 , G06F1/08 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A phase locked loop (PLL) circuit uses a programmable frequency divider (PRFD) to generate a feedback clock from the PLL output clock. The PLL power supply voltage and a PLL reference current are generated by regulating the scalable logic supply voltage of the system in using regulator circuits. The PLL power supply voltage is regulated to a level lower than the lowest level of the scalable logic supply voltage used by the system. The PLL generates a PLL output clock whose frequency is higher than the highest frequency of operation of the system using the highest level of the scalable logic power supply voltage. The PLL output clock is divided is a second PRFD to generate a divided PLL clock. The PLL clock and a fixed auxiliary clock are selected in a glitch-free multiplexer (MUX) as the system clock for the system. The system clock frequency may be dynamically scaled by programming the divisor in the second PRFD dividing the PLL clock. If any of the scaling dynamics may affect the system clock, then the fixed frequency clock may be selected as the system clock until any transients have stabilized. The MUX may also stop the system in a known logic state. The PLL may also be optimized while the system is running.
摘要翻译： 锁相环（PLL）电路使用可编程分频器（PRFD）从PLL输出时钟产生反馈时钟。 通过在调节器电路中调节系统的可伸缩逻辑电源电压来产生PLL电源电压和PLL参考电流。 PLL电源电压调节到低于系统使用的可伸缩逻辑电源电压的最低电平。 PLL产生PLL输出时钟，其频率高于使用最高级别的可伸缩逻辑电源电压的系统的最高工作频率。 PLL输出时钟分为第二个PRFD，用于产生一个分频的PLL时钟。 在无毛刺多路复用器（MUX）中选择PLL时钟和固定辅助时钟作为系统的系统时钟。 可以通过在分频PLL时钟的第二PRFD中对除数进行编程来动态地缩放系统时钟频率。 如果任何缩放动力学可能影响系统时钟，则可以选择固定频率时钟作为系统时钟，直到任何瞬变稳定为止。 MUX还可以以已知的逻辑状态停止系统。 PLL也可以在系统运行时进行优化。
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