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1.发明授权
公开(公告)号：US4156938A
公开(公告)日：1979-05-29
申请号：US644854
申请日：1975-12-29
IPC分类号： G11C11/408 , G11C5/02 , G11C11/404 , G11C11/4097 , G11C11/413 , H01L27/10 , H03M7/00 , G11C8/00
CPC分类号： H03M7/005 , G11C11/404 , G11C11/4097 , G11C5/025
摘要： A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row. The least significant bit of the six column address inputs is used to make the final one out of two selection of the sense amplifier and thus the cell from which data is to be read or in which data is to be written. The decoder includes circuit means for storing the decode signal identifying a selected row while subsequent column address signals are input to the chip and decoded by the same decoder. Row address data is first input through the six address pins to the chip; the six inputs are sampled and latched in six address buffers; and the six address inputs are then decoded so that a single row enable line is selected and held active dynamically. Then while data is read from all storage cells in the active row by the sense amplifiers, column address signals applied to the same input pins for the chip are sampled and latched in the same six address buffers, and decoded by the same decoder to select and hold a column enable line active.
摘要翻译： 公开了具有4,096个二进制存储单元的动态随机存取读/写存储器。 该系统利用一组六个地址输入缓冲器和一个解码器用于行和列地址信息。 存储器阵列包括由64个读出放大器行分隔的动态存储单元的两个32×64阵列，每个具有分离的读出总线或延伸到每列存储器位的数字线。 解码器沿着阵列的与读出放大器行成直角的一个边缘设置。 来自解码器的列使能线通过并行行使能线之间的存储器阵列延伸，然后作为并行数字线之间的不同级别的互连进行转换并选择所寻址的读出放大器。 每列使能线使两个读出放大器同时从寻址行的两个单元读取数据。 六列地址输入的最低有效位用于使读出放大器的两个选择中的最后一位，从而从其读取数据或要写入数据的单元。 解码器包括用于存储识别所选行的解码信号的电路装置，而随后的列地址信号被输入到芯片并由相同的解码器解码。 行地址数据首先通过六个地址引脚输入到芯片; 六个输入被采样并锁存在六个地址缓冲器中; 然后对六个地址输入进行解码，从而动态地选择并保持单行使能线。 然后，当由读出放大器从活动行中的所有存储单元读取数据时，施加到芯片的相同输入引脚的列地址信号被采样并锁存在相同的六个地址缓冲器中，由相同的解码器进行解码以选择和 保持列启用行处于活动状态。
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公开(公告)号：US4096402A
公开(公告)日：1978-06-20
申请号：US644856
申请日：1975-12-29
IPC分类号： H03K5/24 , H03K19/0185 , H03K5/20 , G11C8/00 , H03K5/18
CPC分类号： H03K5/2481 , H03K19/01855
摘要： An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL logic signals of 0.8 volts and 1.8 volts, is trapped on a reference storage node and the logic input voltage is trapped on a data input storage node. The two trapped voltages are then capacitively boosted by the same voltage to a level well above the transistor threshold voltage so that the differences in the voltage levels can be amplified, and the logic signal latched up by conventional circuitry. The voltage levels need be only momentarily boosted above the threshold level. The circuit includes a system for protecting against input voltage undershoot which includes another capacitive input storage node with a first trapping transistor between the logic input to the circuit and the second storage node and a second trapping transistor between the second storage node and the data input storage node. This prevents any degradation of voltage level on the data storage node should the input logic level momentarily be pulled more than one threshold below the level, typically ground, to which the gates of the transistors are taken after the voltage is trapped on the data node.
摘要翻译： 描述用于MOSFET集成电路的输入缓冲器，用于接收低于包括电路的晶体管的阈值电压的低电平电压信号。 输入电压的两个逻辑电平之间的参考电压（例如0.8伏和1.8伏的TTL逻辑信号）被捕获在参考存储节点上，并且逻辑输入电压被捕获在数据输入存储节点上。 然后将两个被俘获的电压通过相同的电压电容地提升到远高于晶体管阈值电压的电平，使得可以放大电压电平的差异，并且由常规电路锁存逻辑信号。 电压电平只能瞬间升高到阈值以上。 该电路包括用于防止输入电压下冲的系统，该系统包括另一个电容性输入存储节点，在电路的逻辑输入与第二存储节点之间具有第一捕获晶体管，以及在第二存储节点和数据输入存储器之间的第二陷阱晶体管 节点。 如果输入逻辑电平暂时被拉到超过在电压被捕获在数据节点上之后获取晶体管的栅极的电平（通常为接地）的一个以上的阈值，则可以防止数据存储节点上的电压电平的任何劣化。
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公开(公告)号：US4328563A
公开(公告)日：1982-05-04
申请号：US136588
申请日：1980-04-02
申请人： Paul R. Schroeder
发明人： Paul R. Schroeder
IPC分类号： H01L21/8246 , H01L27/112 , G11C17/00
CPC分类号： H01L27/1126 , H01L27/112
摘要： The disclosed read only memory is formed in a two-dimensional matrix comprised of active areas disposed in parallel columns and of conductive layers disposed in rows transverse to the columns. A field-effect transistor is formed at each intersection of a column and a row. The rows of conductive layers are closely packed so that adjacent transistor channels abut one another.
摘要翻译： 所公开的只读存储器形成在二维矩阵中，该二维矩阵包括设置在平行列中的有源区和横向于列的排设置的导电层。 在列和行的每个交叉处形成场效应晶体管。 导电层的行紧密堆积，使得相邻的晶体管通道彼此邻接。
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公开(公告)号：US4477739A
公开(公告)日：1984-10-16
申请号：US402395
申请日：1982-07-27
IPC分类号： G11C5/02 , G11C11/404 , G11C11/4097 , H03K19/096 , H03K19/177
CPC分类号： G11C11/4097 , G11C11/404 , G11C5/025
摘要： A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row. The least significant bit of the six column address inputs is used to make the final one out of two selection of the sense amplifier and thus the cell from which data is to be read or in which data is to be written. The decoder includes circuit means for storing the decode signal identifying a selected row while subsequent column address signals are input to the chip and decoded by the same decoder. Row address data is first input through the six address pins to the chip; the six inputs are sampled and latched in six address buffers; and the six address inputs are then decoded so that a single row enable line is selected and held active dynamically. Then while data is read from all storage cells in the active row by the sense amplifiers, column address signals applied to the same input pins for the chip are sampled and latched in the same six address buffers, and decoded by the same decoder to select and hold a column enable line active.
摘要翻译： 公开了具有4,096个二进制存储单元的动态随机存取读/写存储器。 该系统利用一组六个地址输入缓冲器和一个解码器用于行和列地址信息。 存储器阵列包括由64个读出放大器行分隔的动态存储单元的两个32×64阵列，每个具有分离的读出总线或延伸到每列存储器位的数字线。 解码器沿着阵列的与读出放大器行成直角的一个边缘设置。 来自解码器的列使能线通过并行行使能线之间的存储器阵列延伸，然后作为并行数字线之间的不同级别的互连进行转换并选择所寻址的读出放大器。 每列使能线使两个读出放大器同时从寻址行的两个单元读取数据。 六列地址输入的最低有效位用于使读出放大器的两个选择中的最后一位，从而从其读取数据或要写入数据的单元。 解码器包括用于存储识别所选行的解码信号的电路装置，而随后的列地址信号被输入到芯片并由相同的解码器解码。 行地址数据首先通过六个地址引脚输入到芯片; 六个输入被采样并锁存在六个地址缓冲器中; 然后对六个地址输入进行解码，从而动态地选择并保持单行使能线。 然后，当由读出放大器从活动行中的所有存储单元读取数据时，施加到芯片的相同输入引脚的列地址信号被采样并锁存在相同的六个地址缓冲器中，由相同的解码器进行解码以选择和 保持列启用行处于活动状态。
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公开(公告)号：US4061954A
公开(公告)日：1977-12-06
申请号：US741720
申请日：1976-11-08
IPC分类号： G11C11/409 , G11C11/404 , G11C11/4091 , G11C11/4094 , G11C11/24
CPC分类号： G11C11/4094 , G11C11/404 , G11C11/4091
摘要： An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a variable resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V.sub.DD. When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other digit line. As a result, one of the digit lines has a slightly higher voltage than the other. The first set of transistors permit the latching node to be very rapidly brought to ground in order to completely discharge the digit line having the lower voltage, while maintaining substantially the initial high voltage on the other digit line. The common gate nodes of the first transistors are precharged to the drain supply voltage when one of the true or complement digit lines in each column is low and then isolated to provide bootstrapping above V.sub.DD when the digit lines are subsequently precharged to the drain supply voltage of the system. The split digit lines are precharged from a common node through a first pair of transistors, with the common node being charged through a third transistor. The third transistor is turned off before the first pair of transistors to prevent noise in the drain supply voltage from resulting in uneven voltage precharges on the split data lines.
摘要翻译： 公开了一种利用以行和列排列的多个存储单元的集成电路MOSFET动态随机存取存储器。 每列中的一半单元格连接到真数字线，另一半连接到补码数字线。 真和补码数字线各自通过独立的晶体管连接，该晶体管作为可变电阻起到读出放大器的真实和补码输入节点的作用。 读出放大器包括将每个输入节点连接到锁存节点的晶体管，晶体管的栅极交叉耦合到相对的输入节点。 数字线被预充电到对应于VDD的相等电压。 当通过地址信号使能时，存储单元连接到其中一个数字线，同时虚拟单元连接到另一个数字线。 因此，一条数字线的电压比另一条数字线略高。 第一组晶体管允许锁存节点非常迅速地接地，以便完全放电具有较低电压的数字线，同时基本保持另一数字线上的初始高电压。 当每列中的一个真或补数字线为低电平时，第一晶体管的公共栅极节点被预充电到漏极电源电压，然后隔离以在数字线随后预充电到漏极电源电压 系统。 分割数字线通过第一对晶体管从公共节点预充电，公共节点通过第三晶体管被充电。 第三晶体管在第一对晶体管之前被截止，以防止漏极电源电压中的噪声导致分裂数据线上的不均匀的电压预充电。
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公开(公告)号：US4061933A
公开(公告)日：1977-12-06
申请号：US644855
申请日：1975-12-29
CPC分类号： H03K5/1515 , H03K5/13 , H03K5/1504
摘要： A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a source supply voltage, thus forming a first node between the transistors. The first node is capacitively coupled to a bootstrap node which is connected to the gate of the first transistor. The bootstrap node is also coupled through the channel of a third transistor to an input. The gate of the third transistor forms a third node. Circuit means are provided for precharging the third node and then isolating the third node while an input signal is applied through the third transistor to the bootstrap node so that the third node is also bootstrapped up to permit rapid charging of the bootstrap node to the full voltage of the input signal. The second transistor is held on by a precharge signal so that the first node is held low until the bootstrap node has been charged to the input voltage. Then both the third node and the gate of the second transistor are discharged to turn the second and third transistors off, thus permitting the bootstrap node to go rapidly above the drain supply voltage. The bootstrap node may be used directly as output, or can drive the gate of an output transistor so as to produce a very rapidly rising output which quickly reaches the full drain supply voltage. Circuit means is also provided to discharge the third node to disable the output before an input signal occurs. Since the third node is automatically discharged after receiving an input, the input may subsequently be changed without changing the output. Circuit means is also provided to selectively discharge the bootstrap node to isolate the output after it has achieved maximum voltage, so that the output can be capacitively boosted above the drain supply voltage. A circuit is also provided to reset the output to zero volts in conjunction with isolation of the output. A clock generator employing the various functions of a plurality of cascaded delay stages is also disclosed to demonstrate the capabilities of producing a series of clock pulses which go to V.sub.DD in timed sequence in response to input signal, of producing a voltage substantially above V.sub.DD, and of producing a pulse of predetermined duration.
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公开(公告)号：US4296480A
公开(公告)日：1981-10-20
申请号：US066149
申请日：1979-08-13
IPC分类号： G11C11/406 , H03K21/00 , G11C11/40
CPC分类号： H03K21/00 , G11C11/406
摘要： A refresh counter which uses existing address buffers and is implemented with refresh address storage and decoders. The address buffers act to multiplex the refresh address storage outputs as inverted outputs when properly enabled. When all lower order bits are true at a particular unit of the refresh counter and a transfer clock signal occurs, the outputs of the buffer are transferred to the refresh storage where the buffer multiplexes them when enabled. The clocking scheme is structured to enable only at the end of a refresh cycle. In this manner, the counter is incremented at the end of each refresh cycle.
摘要翻译： 一个使用现有地址缓冲区并用刷新地址存储和解码器实现的刷新计数器。 当正确启用时，地址缓冲区用于将刷新地址存储输出复用为反相输出。 当刷新计数器的特定单元的所有低位都为真时，发生传输时钟信号时，缓冲器的输出将被传送到刷新存储器，当缓冲器使能时，缓冲器的多路复用。 时钟方案的结构只能在刷新周期结束时启用。 以这种方式，计数器在每个刷新周期结束时递增。
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公开(公告)号：US4061999A
公开(公告)日：1977-12-06
申请号：US644857
申请日：1975-12-29
IPC分类号： G11C11/409 , G11C11/404 , G11C11/4091 , G11C11/4094 , G11C11/40
CPC分类号： G11C11/4094 , G11C11/404 , G11C11/4091
摘要： An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a varible resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V.sub.DD. When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other line. As a result, one of the digit lines has a slightly higher voltage than the other. The first set of transistors permit the latching node to be very rapidly brought to ground in order to completely discharge the digit line having the lower voltage, while maintaining substantially the initial high voltage on the other digit line. The common gate nodes of the first transistors are precharged to the drain supply voltage when one of the true or complement digit lines in each column is low and then isolated to provide bootstrapping above V.sub.DD when the digit lines are subsequently precharged to the drain supply voltage of the system. The split digit lines are precharged from a common node through a first pair of transistors, with the common node being charged through a third transistor. The third transistor is turned off before the first pair of transistors to prevent noise in the drain supply voltage from resulting in uneven voltage precharges on the split data lines.
摘要翻译： 公开了一种利用以行和列排列的多个存储单元的集成电路MOSFET动态随机存取存储器。 每列中的一半单元格连接到真数字线，另一半连接到补码数字线。 真实和补码数字线各自通过用作读出放大器的真实和补码输入节点的独立晶体管连接，该晶体管起到可变阻抗的作用。 读出放大器包括将每个输入节点连接到锁存节点的晶体管，晶体管的栅极交叉耦合到相对的输入节点。 数字线被预充电到对应于VDD的相等电压。 当通过地址信号使能时，存储单元连接到一条数字线，同时虚拟单元连接到另一条线。 因此，一条数字线的电压比另一条数字线略高。 第一组晶体管允许锁存节点非常迅速地接地，以便完全放电具有较低电压的数字线，同时基本保持另一数字线上的初始高电压。 当每列中的一个真或补数字线为低电平时，第一晶体管的公共栅极节点被预充电到漏极电源电压，然后隔离以在数字线随后预充电到漏极电源电压 系统。 分割数字线通过第一对晶体管从公共节点预充电，公共节点通过第三晶体管被充电。 第三晶体管在第一对晶体管之前被截止，以防止漏极电源电压中的噪声导致分裂数据线上的不均匀的电压预充电。
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公开(公告)号：US4110841A
公开(公告)日：1978-08-29
申请号：US857935
申请日：1977-12-06
申请人： Paul R. Schroeder
发明人： Paul R. Schroeder
IPC分类号： G11C11/4091 , H03K3/356 , G11C7/00
CPC分类号： G11C11/4091 , H03K3/356017 , H03K3/356095
摘要： A low power high sensitivity detector having two pairs of cross coupled transistors and voltage equalization circuitry forms the basic configuration of a detector-level shifter circuit and a sense-refresh detector circuit which are both compatible with today's single chip large capacity MOS memories.
摘要翻译： 具有两对交叉耦合晶体管和电压均衡电路的低功率高灵敏度检测器形成了与当今单芯片大容量MOS存储器兼容的检测器电平移位器电路和感测刷新检测器电路的基本配置。
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