公开(公告)号：US07956432B2

公开(公告)日：2011-06-07

申请号：US12365141

申请日：2009-02-03

申请人： Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

发明人： Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

IPC分类号： H01L21/02

CPC分类号： H01L27/1462 ,  H01L27/1463 ,  H01L31/02165

摘要： A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC comprises at least two different dielectric layers. A layer resistant to oxide etch is above a peripheral portion the multi-layer ARC. Further layers are above the layer resistant to oxide etch, and thereby above the peripheral portion the multi-layer ARC. A window extends down to the multi-layer ARC. A photodiode region is formed by a pn-junction of the first semiconductor type surface region and the second semiconductor type surface layer.

摘要翻译： 光电二极管包括在其至少一部分上具有第一半导体型表面区域的基板和形成在表面区域的一部分中的第二半导体型表面层。 多层抗反射涂层（ARC）在第二半导体型表面层上，其中多层ARC包括至少两个不同的电介质层。 耐氧化物蚀刻的层在多层ARC的外围部分之上。 另外的层在耐氧化物蚀刻层上方，并且因此在多层ARC的周边部分之上。 一个窗口向下延伸到多层ARC。 光电二极管区域由第一半导体型表面区域和第二半导体型表面层的pn结形成。

公开(公告)号：US09355736B1

公开(公告)日：2016-05-31

申请号：US14536975

申请日：2014-11-10

申请人： Perumal Ratnam

发明人： Perumal Ratnam

IPC分类号： G11C16/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of operating a memory device can include accessing at least one memory cell of a memory cell pair formed in opposing vertical sides of an opening by driving at least a first word line common to the memory cell pair to an access voltage to enable a channel conductance in both memory cells of the memory cell pair, driving a selector line, that is vertically aligned with the first word line within the opening, to a selection voltage to enable separate conductive source lines in the opposing vertical sides, and coupling one of the source lines to a source bias voltage and coupling the other of the source lines to a high impedance.

摘要翻译： 操作存储器件的方法可以包括通过将至少存储单元对公共的至少第一字线驱动到访问电压来访问在开口的相对的垂直侧中形成的存储单元对的至少一个存储单元，以使通道 在存储单元对的两个存储单元中的电导，驱动与开口内的第一字线垂直对准的选择器线到选择电压，以使相对的垂直侧中的分离的导电源线能够耦合， 源极线到源偏置电压并将另一个源极线耦合到高阻抗。

公开(公告)号：US08885407B1

公开(公告)日：2014-11-11

申请号：US13009761

申请日：2011-01-19

申请人： Perumal Ratnam

发明人： Perumal Ratnam

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A memory device may include a plurality of cell pairs each including insulator regions interposed between opposing sides of at least one common word line gate and first and second vertical sides formed by a spacing within at least one semiconductor material; and at least one selector gate vertically aligned with the word line gate within the spacing configured to enable first and second source regions in the first and second vertical sides, respectively; wherein when the selector gate is enabled, the first and second source regions are connected to different source diffusion regions.

摘要翻译： 存储器件可以包括多个单元对，每个单元对包括介于至少一个公共字线栅极的相对侧之间的绝缘体区域，以及由至少一个半导体材料内的间隔形成的第一和第二垂直边; 以及在所述间隔内与所述字线栅极垂直对准的至少一个选择栅，所述选择栅分别配置成使得能够分别在所述第一和第二垂直边中的第一和第二源极区域; 其中当选择器栅极被使能时，第一和第二源极区域连接到不同的源极扩散区域。

公开(公告)号：US20120273882A1

公开(公告)日：2012-11-01

申请号：US13095546

申请日：2011-04-27

申请人： PERUMAL RATNAM

发明人： PERUMAL RATNAM

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0634 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66704 ,  H01L29/66787 ,  H01L29/7825

摘要： A novel lateral super junction device compatible with standard CMOS processing techniques using shallow trench isolation is provided for low- and medium-voltage power management applications. The concept is similar to other lateral super junction devices having N- and P-type implants to deplete laterally to sustain the voltage. However, the use of shallow trench structures provides the additional advantage of reducing the Rdson without the loss of the super junction concept and, in addition, increasing the effective channel width of the device to form a “FINFET” type structure, in which the conducting channel is wrapped around a thin silicon “fin” that forms the body of the device. The device is manufactured using standard CMOS processing techniques with the addition of super junction implantation steps, and the addition of polysilicon within the shallow trench structures to form fin structures.

摘要翻译： 提供了与使用浅沟槽隔离的标准CMOS处理技术兼容的新型横向超接线器件用于低压和中压电源管理应用。 该概念类似于具有N型和P型植入物以横向消耗以维持电压的其它横向超连接装置。 然而，使用浅沟槽结构提供了减少Rdson而没有超连接概念的损失的附加优点，此外，增加器件的有效沟道宽度以形成FINFET型结构，其中导通沟道是 缠绕在形成装置主体的薄硅片上。 该器件使用标准CMOS处理技术制造，其中添加超结注入步骤，以及在浅沟槽结构内添加多晶硅以形成鳍结构。

公开(公告)号：US06236608B1

公开(公告)日：2001-05-22

申请号：US09375702

申请日：1999-08-16

申请人： Perumal Ratnam

发明人： Perumal Ratnam

IPC分类号： G11C1300

CPC分类号： G11C16/14

摘要： In one aspect, the present invention provides a method for erasing a semiconductor device that comprises applying a voltage pulse at the source of the semiconductor device and a multiple step voltage pulse of the opposite polarity at the gate of the semiconductor device. The multiple step voltage pulse comprises at least a first voltage pulse and a second voltage pulse at the gate of the semiconductor device. The second voltage pulse is usually greater in magnitude than the first voltage pulse. In another aspect, the present invention provides a method for erasing a semiconductor device that comprises applying a substantially constant positive voltage pulse for a first time interval, t1, at the source of the semiconductor device. A first and then a second negative voltage pulse are also applied at the gate of the semiconductor device for a second and third time interval, t2 and t3, respectively. The second negative voltage pulse is greater in magnitude than the first negative voltage pulse. The negative and positive voltage pulses are substantially coincident in time.

摘要翻译： 一方面，本发明提供一种擦除半导体器件的方法，该半导体器件包括在半导体器件的源极处施加电压脉冲，并在半导体器件的栅极处施加相反极性的多级电压脉冲。 多级电压脉冲在半导体器件的栅极处包括至少第一电压脉冲和第二电压脉冲。 第二电压脉冲的幅度通常大于第一电压脉冲。 另一方面，本发明提供了一种擦除半导体器件的方法，该方法包括在半导体器件的源极处施加基本恒定的正电压脉冲，该第一时间间隔t1。 第一和第二负电压脉冲也分别在第二和第三时间间隔t2和t3施加在半导体器件的栅极处。 第二负电压脉冲的幅度大于第一负电压脉冲。 负电压和正电压脉冲在时间上基本一致。

公开(公告)号：US20130011985A1

公开(公告)日：2013-01-10

申请号：US13550235

申请日：2012-07-16

申请人： Perumal RATNAM

发明人： Perumal RATNAM

IPC分类号： H01L21/336

CPC分类号： H01L29/0634 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66704 ,  H01L29/66787 ,  H01L29/7825

摘要： A novel lateral super junction device compatible with standard CMOS processing techniques using shallow trench isolation is provided for low- and medium-voltage power management applications. The concept is similar to other lateral super junction devices having N- and P-type implants to deplete laterally to sustain the voltage. However, the use of shallow trench structures provides the additional advantage of reducing the Rdson without the loss of the super junction concept and, in addition, increasing the effective channel width of the device to form a “FINFET” type structure, in which the conducting channel is wrapped around a thin silicon “fin” that forms the body of the device. The device is manufactured using standard CMOS processing techniques with the addition of super junction implantation steps, and the addition of polysilicon within the shallow trench structures to form fin structures.

摘要翻译： 提供了与使用浅沟槽隔离的标准CMOS处理技术兼容的新型横向超接线器件用于低压和中压电源管理应用。 该概念类似于具有N型和P型植入物以横向消耗以维持电压的其它横向超连接装置。 然而，使用浅沟槽结构提供了减少Rdson而没有超连接概念的损失的附加优点，此外，增加器件的有效沟道宽度以形成FINFET型结构，其中导通沟道是 缠绕在形成装置主体的薄硅片上。 该器件使用标准CMOS处理技术制造，其中添加超结注入步骤，以及在浅沟槽结构内添加多晶硅以形成鳍结构。

公开(公告)号：US20090174021A1

公开(公告)日：2009-07-09

申请号：US12365141

申请日：2009-02-03

申请人： Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

发明人： Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

IPC分类号： H01L31/0232

CPC分类号： H01L27/1462 ,  H01L27/1463 ,  H01L31/02165

摘要： A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC comprises at least two different dielectric layers. A layer resistant to oxide etch is above a peripheral portion the multi-layer ARC. Further layers are above the layer resistant to oxide etch, and thereby above the peripheral portion the multi-layer ARC. A window extends down to the multi-layer ARC. A photodiode region is formed by a pn-junction of the first semiconductor type surface region and the second semiconductor type surface layer.

摘要翻译： 光电二极管包括在其至少一部分上具有第一半导体型表面区域的基板和形成在表面区域的一部分中的第二半导体型表面层。 多层抗反射涂层（ARC）在第二半导体型表面层上，其中多层ARC包括至少两个不同的电介质层。 耐氧化物蚀刻的层在多层ARC的外围部分之上。 另外的层在耐氧化物蚀刻层上方，并且因此在多层ARC的周边部分之上。 一个窗口向下延伸到多层ARC。 光电二极管区域由第一半导体型表面区域和第二半导体型表面层的pn结形成。

公开(公告)号：US06456537B1

公开(公告)日：2002-09-24

申请号：US09870050

申请日：2001-05-29

申请人： Perumal Ratnam

发明人： Perumal Ratnam

IPC分类号： G11C1604

CPC分类号： G11C16/344 ,  G11C16/14 ,  G11C16/16

摘要： Techniques for improved erasing of an EPROM are described. As a method, a a drain potential of a first polarity is applied to the drain node of a selected memory cell having a first polarity concurrently with applying a gate potential of a second polarity to the gate of the selected memory cell having a second polarity. The drain and the gate polarities are then maintained until the charge has been removed from the floating gate structure of the selected memory cell as determined by a verification protocol.

摘要翻译： 描述了用于改进EPROM擦除的技术。 作为一种方法，将第一极性的漏极电位施加到具有第一极性的选定存储单元的漏极节点，同时将具有第二极性的栅极电位施加到具有第二极性的选定存储单元的栅极。 然后维持漏极和栅极极性，直到通过验证方案确定的电荷已经从所选择的存储单元的浮动栅极结构去除。

公开(公告)号：US06429076B2

公开(公告)日：2002-08-06

申请号：US09766971

申请日：2001-01-22

申请人： Perumal Ratnam ,  Ritu Shrivastava

发明人： Perumal Ratnam ,  Ritu Shrivastava

IPC分类号： H01L218247

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L29/42324

摘要： A flash EPROM cell (10) is disclosed having increased capacitive coupling between a floating gate (28) and a control gate (32). Vertical structural elements (34a and 34b) are formed on field oxide regions (20) on opposing sides of the flash EPROM cell channel 20, in the channel width direction. The structural elements (34a and 34b) include relatively vertical faces. The floating gate (28) conformally cover the channel 20 and the vertical faces of the structural elements (34a and 34b). The control gate (32) conformally covers the floating gate (28). The vertical displacement introduced by the structural elements (34a and 34b) increases the overlap area between the floating gate (28) and the control gate (32) without increasing the overlap area of the floating gate (28) and the channel 20, resulting in increased capacitive coupling between the control gate (32) and the floating gate (28). A process is disclosed which enables the formation of the above structural elements (34a and 34b) with dimensions that are smaller than those normally achievable by the minimum resolution of lithography equipment.

摘要翻译： 公开了一种闪存EPROM单元（10），其具有在浮动栅极（28）和控制栅极（32）之间增加的电容耦合。 垂直结构元件（34a和34b）在通道宽度方向上形成在闪速EPROM单元通道20的相对侧的场氧化物区域（20）上。 结构元件（34a和34b）包括相对垂直的面。 浮动门（28）共形地覆盖通道20和结构元件（34a和34b）的垂直面。 控制门（32）共形地覆盖浮动门（28）。 由结构元件（34a和34b）引入的垂直位移增加了浮动栅极（28）和控制栅极（32）之间的重叠面积，而不增加浮动栅极（28）和沟道20的重叠面积，导致 增加了控制栅极（32）和浮动栅极（28）之间的电容耦合。 公开了一种能够形成上述结构元件（34a和34b）的方法，其尺寸小于通过光刻设备的最小分辨率通常可达到的尺寸。

公开(公告)号：US5338695A

公开(公告)日：1994-08-16

申请号：US981188

申请日：1992-11-24

申请人： Perumal Ratnam

发明人： Perumal Ratnam

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/762 ,  H01L29/10 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L21/76202 ,  H01L29/1004 ,  H01L29/732

摘要： An improved, walled-emitter, bipolar transistor and a method for fabricating such a transistor is disclosed. The method includes the step of separately doping the edges of the active base that are adjacent to the isolation oxide in order to increase the doping level at the edges and thus counteract base narrowing that would otherwise be present.

摘要翻译： 公开了一种改进的壁发射极双极晶体管和制造这种晶体管的方法。 该方法包括分别掺杂与隔离氧化物相邻的有源基极边缘的步骤，以增加边缘处的掺杂水平，从而抵消否则将存在的基极窄化。