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公开(公告)号：US20050237804A1
公开(公告)日：2005-10-27
申请号：US11170880
申请日：2005-06-30
申请人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
发明人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
CPC分类号： G11C7/24 , G11C16/22 , G11C2029/4402
摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.
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公开(公告)号：US5844839A
公开(公告)日：1998-12-01
申请号：US684962
申请日：1996-07-19
IPC分类号： G11C16/12 , H01L21/8247 , H01L27/105 , G11C11/34 , G11C7/00
CPC分类号： H01L27/11526 , G11C16/12 , H01L27/105 , H01L27/11546
摘要： A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected. The decoder circuit also includes a high power pass device 82 associated with each row line, having one of its source and drain connected to the associated row node, having the other of its source and drain connected to a row line and having its gate connected to a first voltage, lower than the high voltage, so as to couple the signal on the row node to the row line. Finally, a keeper circuit 102 is provided, associated with each row line and coupled to the high voltage for sensing the signal on the row line and in response thereto for coupling the high voltage to the row line. The memory has high speed, since the decoder logic is performed by low power devices. In addition, in fabrication the memory is readily convertible to a permanent ROM by eliminating the formation of the floating gate, bypassing the high power pass device and not connecting the keeper circuit.
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公开(公告)号：US07028135B2
公开(公告)日：2006-04-11
申请号：US10229924
申请日：2002-08-28
IPC分类号： G06F12/00
CPC分类号： G11C16/06
摘要： A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.
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公开(公告)号：US06618291B2
公开(公告)日：2003-09-09
申请号：US09803047
申请日：2001-03-12
IPC分类号： G11C1604
CPC分类号： G11C16/10
摘要： A system and method for a write state machine for non-volatile memory is disclosed. The system includes an array of memory cells and a write state machine for controlling operations on the array of memory cells. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory. The write state machine is adapted to suspend an execution of one of the operations during an action on a block in the non-volatile memory which is not being accessed by the write state machine.
摘要翻译： 公开了一种用于非易失性存储器的写状态机的系统和方法。 该系统包括存储器单元阵列和用于控制存储器单元阵列上的操作的写状态机。 写状态机具有用于存储用于非易失性存储器的操作的指令的相关联的只读存储器。 写入状态机适用于在非易失性存储器中由写入状态机未被访问的块上的动作期间暂停执行其中一个操作。
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公开(公告)号：US07145799B2
公开(公告)日：2006-12-05
申请号：US11170880
申请日：2005-06-30
申请人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
发明人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
IPC分类号： G11C16/22
CPC分类号： G11C7/24 , G11C16/22 , G11C2029/4402
摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.
摘要翻译： 用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。 当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。 这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。 这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。 此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。
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公开(公告)号：US06947323B2
公开(公告)日：2005-09-20
申请号：US10698752
申请日：2003-10-31
申请人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
发明人： Giovanni Naso , Pietro Piersimoni , Tommaso Vali
CPC分类号： G11C7/24 , G11C16/22 , G11C2029/4402
摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.
摘要翻译： 用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。 当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。 这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。 这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。 此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。
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公开(公告)号：US20050195655A1
公开(公告)日：2005-09-08
申请号：US11123184
申请日：2005-05-06
CPC分类号： G11C16/16 , G11C2216/20
摘要： A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.
摘要翻译： 公开了一种用于非易失性存储器的写状态机的系统和方法。 写状态机具有用于存储用于非易失性存储器的操作的指令的相关联的只读存储器。
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公开(公告)号：US5874849A
公开(公告)日：1999-02-23
申请号：US684652
申请日：1996-07-19
CPC分类号： H02M3/073
摘要： A charge pump 1 for operation in an integrated circuit having a power source Vdd. The pump is made of a plurality of pump cells 10 connected together. Each pump cell includes an inverter 50 having a port 42 to receive a negative bias input, a port 44 to receive a positive bias input, a port 38 to receive a clock input, and a port 40 to output an output clock signal at the same frequency of the clock input, but phase shifted by a predetermined amount determined by the signal levels of the negative bias and said positive bias. Also included in each pump cell is a capacitor 26. A circuit 20, 22, 24, for coupling the output clock signal to one port of the capacitor is also provided, as is a pair of diodes 28, 30, connected serially together, one end of the pair being connected to the power source and the other end 48 of the pair providing the output signal of the pump cell, the common point of the pair being connected to the other port of the capacitor. The pump cells are connected together such that the inverters are connected together to form a ring oscillator and such that the output signals are connected in parallel. The pump provides a stable source of high current at a moderately boosted voltage, with very low ripple, and is suitable for use with non-volatile, programmable memories.
摘要翻译： 一种用于在具有电源Vdd的集成电路中操作的电荷泵1。 泵由连接在一起的多个泵电池10制成。 每个泵单元包括具有端口42以接收负偏置输入的反相器50，用于接收正偏压输入的端口44，用于接收时钟输入的端口38和用于输出时钟输入的端口40以输出相同的输出时钟信号 时钟输入的频率，但是相移了由负偏压和所述正偏压的信号电平确定的预定量。 还包括在每个泵浦单元中的是电容器26.还提供用于将输出时钟信号耦合到电容器的一个端口的电路20,22,24，以及串联连接在一起的一对二极管28,30，一个 该对的端部连接到电源，并且该对的另一端48提供泵电池的输出信号，该对的公共点连接到电容器的另一个端口。 泵电池连接在一起，使得逆变器连接在一起以形成环形振荡器，并且使得输出信号并联连接。 该泵在适中的升压电压下提供稳定的高电流源，具有非常低的纹波，适用于非易失性可编程存储器。
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公开(公告)号：US5715195A
公开(公告)日：1998-02-03
申请号：US683943
申请日：1996-07-19
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A method for automatically detecting and correcting the underprogramming of a memory cell 10 in a non-volatile, progrommable memory array 1, the array having a plurality of such cells, each such cell being programmable by a progromming step that stores charge therein and being erasable by an erasing step that removes charge therefrom, and each such cell being readable to determine whether such cell is in a progrommed state or in an erased state. First, charge is stored in a selected cell therein 74. Then the selected cell is read to determine whether the selected cell is programmed 78. If the step of reading does not determine such cell to be programmed 80, the steps of storing and reading are automatically repeated until either the step of sensing indicates a sufficiently programmed cell or, alternatively, until a predermined number of iterations of the steps has been performed 86.
摘要翻译： 一种用于在非易失性可编程存储器阵列1中自动检测和校正存储器单元10的欠编程的方法，所述阵列具有多个这样的单元，每个这样的单元可以通过在其中存储电荷并且是可擦除的编程步骤来编程 通过从其中去除电荷的擦除步骤，并且每个这样的单元是可读取的，以确定这样的单元是处于预占状态还是处于擦除状态。 首先，将电荷存储在其中的所选择的单元中。然后读取所选择的单元，以确定所选择的单元是否被编程78.如果读取步骤不确定这样的要被编程的单元80，则存储和读取的步骤是 自动重复，直到感测步骤指示足够编程的单元，或者替代地，直到已经执行步骤的迭代次数已被执行86。
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公开(公告)号：US07136307B2
公开(公告)日：2006-11-14
申请号：US11123184
申请日：2005-05-06
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C2216/20
摘要： A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.
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