公开(公告)号：US07879708B2

公开(公告)日：2011-02-01

申请号：US11534143

申请日：2006-09-21

Applicant: Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

Inventor： Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract translation: 一种用于制造浮动栅极存储器件的方法包括使用在浮置栅极之下的掩埋扩散氧化物，从而在浮置栅极和掩埋扩散氧化物之间产生增加的台阶高度。 增加的台阶高度可以产生更高的GCR，而仍然允许使用虚拟接地阵列设计减小单元尺寸。

公开(公告)号：US20080121971A1

公开(公告)日：2008-05-29

申请号：US11534143

申请日：2006-09-21

Applicant: Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

Inventor： Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract translation: 一种用于制造浮动栅极存储器件的方法包括使用在浮置栅极之下的掩埋扩散氧化物，从而在浮置栅极和掩埋扩散氧化物之间产生增加的台阶高度。 增加的台阶高度可以产生更高的GCR，而仍然允许使用虚拟接地阵列设计减小单元尺寸。

公开(公告)号：US20110086482A1

公开(公告)日：2011-04-14

申请号：US12975737

申请日：2010-12-22

Applicant: Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

Inventor： Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

IPC: H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract translation: 一种用于制造浮动栅极存储器件的方法包括使用在浮置栅极之下的掩埋扩散氧化物，从而在浮置栅极和掩埋扩散氧化物之间产生增加的台阶高度。 增加的台阶高度可以产生更高的GCR，而仍然允许使用虚拟接地阵列设计减小单元尺寸。

公开(公告)号：US08354335B2

公开(公告)日：2013-01-15

申请号：US12975737

申请日：2010-12-22

Applicant: Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

Inventor： Chen-Chin Liu ,  Lan Ting Huang ,  Ling Kuey Yang ,  Po Hsuan Wu

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract translation: 一种用于制造浮动栅极存储器件的方法包括使用在浮置栅极之下的掩埋扩散氧化物，从而在浮置栅极和掩埋扩散氧化物之间产生增加的台阶高度。 增加的台阶高度可以产生更高的GCR，而仍然允许使用虚拟接地阵列设计减小单元尺寸。

公开(公告)号：US07367491B2

公开(公告)日：2008-05-06

申请号：US10912856

申请日：2004-08-06

Applicant: Kung Chieh Cheng ,  Po Hsuan Wu

Inventor： Kung Chieh Cheng ,  Po Hsuan Wu

IPC: G06F7/00

CPC classification number: G06Q10/06 ,  G06Q10/06398 ,  G06Q10/10 ,  G06Q10/1091

Abstract: A system for dynamically controlling attendance of a group of employees includes a corporation website (12), an application server (13), a database (15), and a number of client computers (10). The application server includes an attendance management module (131) for performing operations of recording an arrival time, a departure time and a work place of each employee, calculating actual work hours according to the arrival time and departure time, comparing the actual work hours to normal work hours specified in corresponding attendance requirements, and processing abnormal attendance statuses. A related method for dynamically controlling attendance of a group of employees is also disclosed.

Abstract translation: 用于动态地控制一组员工的考勤的系统包括公司网站（12），应用服务器（13），数据库（15）和多个客户端计算机（10）。 应用服务器包括一个出勤管理模块（131），用于执行记录每个员工的到达时间，出发时间和工作地点的操作，根据到达时间和出发时间计算实际工作时间，将实际工作时间与 正常工作时间在相应的出勤要求中规定，并处理异常出勤状态。 还披露了一组动态控制员工出勤率的相关方法。

公开(公告)号：US07286396B2

公开(公告)日：2007-10-23

申请号：US11248506

申请日：2005-10-12

Applicant: Ling Kuey Yang ,  Chen Chin Liu ,  Lan Ting Huang ,  Po Hsuan Wu

Inventor： Ling Kuey Yang ,  Chen Chin Liu ,  Lan Ting Huang ,  Po Hsuan Wu

IPC: G11C11/40

CPC classification number: G11C7/18 ,  H01L27/105 ,  H01L29/4238

Abstract: A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit line loading uniformity and provide greater uniformity in bit line bias. Additionally, the greater uniformity in bit line bias can improve reliability.