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    PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL CONVERTERS
    2.
    发明申请
    PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL CONVERTERS 有权
    可编程多个供电区域，具有开关门级电平转换器

    公开(公告)号：US20080094105A1

    公开(公告)日：2008-04-24

    申请号：US11548206

    申请日：2006-10-10

    申请人： Vikram Santurkar ,  Ravi Thiruveedhula ,  Hyun Yi

    发明人： Vikram Santurkar ,  Ravi Thiruveedhula ,  Hyun Yi

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018521 ,  H03K19/094

    摘要： A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

    摘要翻译： 提供了一种电平转换架构，其适应在以相应电压电平工作的逻辑块之间行进的信号。 该架构包括在逻辑块之间串联连接的通道。 通过门的一个门提供可选择的栅极电压源。 基于配置随机存取存储器（CRAM）设置从多个电压中选择可选择的栅极电压源。 在一个实施例中，半锁存器连接到一个通过门。 在该实施例中，半锁存器是反馈回路的一部分，以最小化逻辑块之一中的逻辑元件的功率泄漏。 还提供了一种用于管理功率消耗并在集成电路的区域之间提供电压电平转换的方法。

    Programmable multiple supply regions with switched pass gate level converters
    3.
    发明授权
    Programmable multiple supply regions with switched pass gate level converters 有权
    可编程多个供电区域，具有开关栅极电平转换器

    公开(公告)号：US07855574B2

    公开(公告)日：2010-12-21

    申请号：US11548206

    申请日：2006-10-10

    申请人： Vikram Santurkar ,  Ravi Thiruveedhula ,  Hyun Yi

    发明人： Vikram Santurkar ,  Ravi Thiruveedhula ,  Hyun Yi

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018521 ,  H03K19/094

    摘要： A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

    摘要翻译： 提供了一种电平转换架构，其适应在以相应电压电平工作的逻辑块之间行进的信号。 该架构包括在逻辑块之间串联连接的通道。 通过门的一个门提供可选择的栅极电压源。 基于配置随机存取存储器（CRAM）设置从多个电压中选择可选择的栅极电压源。 在一个实施例中，半锁存器连接到一个通过门。 在该实施例中，半锁存器是反馈回路的一部分，以最小化逻辑块之一中的逻辑元件的功率泄漏。 还提供了一种用于管理功率消耗并在集成电路的区域之间提供电压电平转换的方法。

    Apparatus and methods for low-power routing circuitry in programmable logic devices
    4.
    发明申请
    Apparatus and methods for low-power routing circuitry in programmable logic devices 审中-公开
    用于可编程逻辑器件中的低功率路由电路的装置和方法

    公开(公告)号：US20070008004A1

    公开(公告)日：2007-01-11

    申请号：US11244572

    申请日：2005-10-06

    申请人： Vikram Santurkar ,  Ravi Thiruveedhula

    发明人： Vikram Santurkar ,  Ravi Thiruveedhula

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/0008 ,  H03K19/17736 ,  H03K19/17784

    摘要： An interconnect circuit includes a driver circuit and a receiver circuit. The receiver circuit couples to the driver circuit. The driver circuit is configured to receive an input signal and to derive from the input signal a limited swing driver output signal. The receiver circuit is configured to derive from the limited swing driver output signal a limited swing receiver output signal.

    摘要翻译： 互连电路包括驱动电路和接收器电路。 接收器电路耦合到驱动器电路。 驱动器电路被配置为接收输入信号并且从输入信号导出有限的摆动驱动器输出信号。 接收器电路被配置为从有限的摆动驱动器输出信号导出有限的摆动接收器输出信号。