公开(公告)号：US5982659A

公开(公告)日：1999-11-09

申请号：US779998

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

发明人： V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/14

CPC分类号： G11C17/00 ,  G11C11/56 ,  G11C11/5692 ,  G11C7/16

摘要： A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

摘要翻译： 能够在存储器单元中存储多于两个逻辑状态的过程。 在一个实施例中，通孔用于在字读取线和数据读取线之间耦合二极管。 通孔具有在制造时被设置为多个值之一的电阻。 当字读取线被断言时，贯穿通孔的电压降指示存储的逻辑状态。 模数（A / D）转换器耦合到数据读取线，以便感测电压降并确定所表示的状态。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。

公开(公告)号：US5045726A

公开(公告)日：1991-09-03

申请号：US524329

申请日：1990-05-16

申请人： Raymond T. Leung

发明人： Raymond T. Leung

IPC分类号： G11C17/18

CPC分类号： G11C17/18

摘要： A programming circuit for an array of bipolar transistors which is selectable by row and column decoders to form a selected logic circuit, programming being effected by thermal links respectively connected to the respective transistors and which undergo a change in conductive state when subjected to a programming current of sufficient magnitude. The programming circuit includes a row driver having an FET gate which in response to a row address selection pulse turns on a bipolar transistor (Q1), the FET gate otherwise maintaining Q1 off. Transistor Q1 forms a Darlington pair with any of the transistors in the corresponding row of the array which are turned on. The transistors in respective columns of the array are connected in common by respective column conductors to respective transmission gates, each transmission gate including another Darlington bipolar pair driven by a CMOS inverter. The inverter opens the transmission gate in response to a strobe pulse which is concurrent with a column selection pulse from the column decoder, but otherwise maintains the transmission gate closed. A significant reduction in power consumption, and consequent heat dissipation, is achieved because the row drivers and transmission gates for non-selected rows and columns do not require quiescent operating current, and programming current for a selected transistor is supplied in a path comprising only bipolar Darlington pairs.

摘要翻译： 一种用于双列晶体管阵列的编程电路，其可由行和列解码器选择以形成选定的逻辑电路，编程由分别连接到相应晶体管的热连接器进行，并且当经受编程电流时，其经历导通状态的变化 足够大。 编程电路包括具有FET栅极的行驱动器，其响应于行地址选择脉冲导通双极晶体管（Q1），FET栅极否则保持Q1截止。 晶体管Q1与导通的阵列的相应行中的任何晶体管形成达林顿对。 阵列的相应列中的晶体管被​​相应的列导体共同连接到相应的传输门，每个传输门包括由CMOS反相器驱动的另一达林顿双极对。 反相器响应于与列解码器的列选择脉冲并发的选通脉冲打开传输门，但是否则保持传输门关闭。 由于用于非选择的行和列的行驱动器和传输门不需要静态工作电流，所以功耗的显着降低以及随之而来的散热得以实现，并且所选晶体管的编程电流仅以双极性 达林顿对。

公开(公告)号：US5847990A

公开(公告)日：1998-12-08

申请号：US779993

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/41 ,  G11C11/56 ,  G11C11/00

CPC分类号： G11C11/5621 ,  G11C11/412 ,  G11C7/16

摘要： A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

摘要翻译： 一种能够在存储单元中存储三种逻辑状态的存储电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由三态触发器的状态决定。 通过使电流被检测为正，负或零，可以用触发器的状态表示多于一个位的信息。

公开(公告)号：US5761110A

公开(公告)日：1998-06-02

申请号：US779992

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/56 ,  G11C17/14

CPC分类号： G11C11/56

摘要： A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

摘要翻译： 一种允许在存储器单元中存储两个以上逻辑状态的系统和过程。 在一个实施例中，可编程电阻器与电源电压和数据读取线之间的晶体管串联耦合。 当访问信号被断言时，晶体管提供导电路径，并且由可编程电阻器维持电压降。 可编程电阻器具有在编程步骤期间通过使加热电流通过可编程电阻器的多个预定时间段中的一个来设定的电阻。 当访问信号被断言时，跨可编程电阻器持续的电压降指示存储的逻辑状态。 模数（A / D）转换器耦合到数据读取线，以便感测电压降并确定所表示的状态。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加存储密度并降低每位的成本。

公开(公告)号：US5867423A

公开(公告)日：1999-02-02

申请号：US838799

申请日：1997-04-10

申请人： Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

发明人： Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/112

CPC分类号： G11C11/5692 ,  G11C7/16

摘要： A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.

摘要翻译： 根据本发明，通过选择性地设置存储器阵列中的晶体管的阈值电压，能够在存储器单元中存储多于两个逻辑状态的电路和方法。 在一个实施例中，存储电路包括存储晶体管阵列。 每个存储晶体管具有连接到相关读取线的栅极。 当读线被确认时，流经所选择的存储晶体管的电流指示存储的逻辑状态。 通过在制造期间设置每个存储晶体管的阈值电压来分别选择通过每个晶体管的电流。 阵列中的不同晶体管配置有不同的阈值电压，从而表示不同的存储状态。 模数（A / D）转换器耦合到选定的存储晶体管，以便感测电流并确定所表示的状态。 由于每个单元可以表示多于两个存储状态之一，所以存储器电路可以有利地允许将更多数量的位存储在每个存储单元中，从而增加存储密度并降低每位的成本。

公开(公告)号：US5808932A

公开(公告)日：1998-09-15

申请号：US779991

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/41 ,  G11C11/56 ,  G11C11/24

CPC分类号： G11C11/565 ,  G11C7/16

摘要： A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

摘要翻译： 一种能够在存储器单元中存储多于两个逻辑状态的存储器电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由存储在晶体管门上的电荷决定。 通过使能够以离散增量检测电流，可以用存储在存储单元中的电荷来表示多于一位的信息。 额外增量的使用需要更精确的存储和检测电路。 在一个实施例中，存储电路使用反馈来获得更大的逻辑状态检索精度。