公开(公告)号：US5982659A

公开(公告)日：1999-11-09

申请号：US779998

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

发明人： V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/14

CPC分类号： G11C17/00 ,  G11C11/56 ,  G11C11/5692 ,  G11C7/16

摘要： A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

摘要翻译： 能够在存储器单元中存储多于两个逻辑状态的过程。 在一个实施例中，通孔用于在字读取线和数据读取线之间耦合二极管。 通孔具有在制造时被设置为多个值之一的电阻。 当字读取线被断言时，贯穿通孔的电压降指示存储的逻辑状态。 模数（A / D）转换器耦合到数据读取线，以便感测电压降并确定所表示的状态。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。

公开(公告)号：US5761110A

公开(公告)日：1998-06-02

申请号：US779992

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/56 ,  G11C17/14

CPC分类号： G11C11/56

摘要： A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

摘要翻译： 一种允许在存储器单元中存储两个以上逻辑状态的系统和过程。 在一个实施例中，可编程电阻器与电源电压和数据读取线之间的晶体管串联耦合。 当访问信号被断言时，晶体管提供导电路径，并且由可编程电阻器维持电压降。 可编程电阻器具有在编程步骤期间通过使加热电流通过可编程电阻器的多个预定时间段中的一个来设定的电阻。 当访问信号被断言时，跨可编程电阻器持续的电压降指示存储的逻辑状态。 模数（A / D）转换器耦合到数据读取线，以便感测电压降并确定所表示的状态。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加存储密度并降低每位的成本。

公开(公告)号：US5867423A

公开(公告)日：1999-02-02

申请号：US838799

申请日：1997-04-10

申请人： Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

发明人： Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/112

CPC分类号： G11C11/5692 ,  G11C7/16

摘要： A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.

摘要翻译： 根据本发明，通过选择性地设置存储器阵列中的晶体管的阈值电压，能够在存储器单元中存储多于两个逻辑状态的电路和方法。 在一个实施例中，存储电路包括存储晶体管阵列。 每个存储晶体管具有连接到相关读取线的栅极。 当读线被确认时，流经所选择的存储晶体管的电流指示存储的逻辑状态。 通过在制造期间设置每个存储晶体管的阈值电压来分别选择通过每个晶体管的电流。 阵列中的不同晶体管配置有不同的阈值电压，从而表示不同的存储状态。 模数（A / D）转换器耦合到选定的存储晶体管，以便感测电流并确定所表示的状态。 由于每个单元可以表示多于两个存储状态之一，所以存储器电路可以有利地允许将更多数量的位存储在每个存储单元中，从而增加存储密度并降低每位的成本。

公开(公告)号：US5808932A

公开(公告)日：1998-09-15

申请号：US779991

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/41 ,  G11C11/56 ,  G11C11/24

CPC分类号： G11C11/565 ,  G11C7/16

摘要： A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

摘要翻译： 一种能够在存储器单元中存储多于两个逻辑状态的存储器电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由存储在晶体管门上的电荷决定。 通过使能够以离散增量检测电流，可以用存储在存储单元中的电荷来表示多于一位的信息。 额外增量的使用需要更精确的存储和检测电路。 在一个实施例中，存储电路使用反馈来获得更大的逻辑状态检索精度。

公开(公告)号：US5847990A

公开(公告)日：1998-12-08

申请号：US779993

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/41 ,  G11C11/56 ,  G11C11/00

CPC分类号： G11C11/5621 ,  G11C11/412 ,  G11C7/16

摘要： A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

摘要翻译： 一种能够在存储单元中存储三种逻辑状态的存储电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由三态触发器的状态决定。 通过使电流被检测为正，负或零，可以用触发器的状态表示多于一个位的信息。

公开(公告)号：US5784328A

公开(公告)日：1998-07-21

申请号：US779999

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/406 ,  G11C11/56 ,  G11C7/00

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/565 ,  G11C16/3418 ,  G11C16/3431

摘要： A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized.

摘要翻译： 一种DRAM存储器阵列，包括用于根据温度调节刷新率的温度传感器。 DRAM存储器阵列包括多个存储器单元，每个存储器单元被配置为允许存储和检索多于两个的离散存储器状态。 刷新电路耦合到存储器阵列，用于周期性地刷新每个存储单元的离散存储状态。 温度传感器位于制造存储器阵列的相同的​​半导体管芯上，并且产生表示半导体管芯的温度的信号。 控制电路接收来自温度传感器的信号，并且响应地产生刷新率信号，该信号被提供以控制刷新电路的刷新率。 在一个具体实现中，ROM查找表耦合到控制电路，并且包括指示特定温度的期望刷新率的多个条目。 通过根据半导体管芯的温度控制刷新率，确保每个存储单元内的适当的状态保持，同时允许优化性能。

公开(公告)号：US5987632A

公开(公告)日：1999-11-16

申请号：US852692

申请日：1997-05-07

申请人： V. Swamy Irrinki ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Thomas R. Wik

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44 ,  G06F11/00 ,  G11C7/00

CPC分类号： G11C29/72 ,  G11C29/44 ,  G11C29/78 ,  G11C2029/0405

摘要： A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry. The test suite may then be re-executed, and the device deemed defective if additional errors are found. Rows and columns in the memory array that are prone to failure are thus never enabled. Additionally, the BIST and BISR circuitry provides the ability to verify basic memory functionality and remap failing addresses on each application of power to the device. Test coverage of the memory array is advantageously increased.

摘要翻译： 用于存储器件的测试方法，其中仅在特定最坏情况条件下发生的故障被转换为硬功能故障。 随后通过内置自检（BIST）和内置自修复（BISR）电路检测和重新映射这些位置。 首先，在包含冗余行和列位置的存储器阵列上执行测试套件。 通常，该测试套件在最有可能引起故障的条件下执行。 被确定为故障的行和列位置以及可用的冗余行和列的数量被扫描出存储器设备。 如果有足够的冗余位置，则通过吹动每个相应的熔丝链，永久禁用故障行和列。 当随后将功率应用于存储设备时，BIST将检测具有硬功能故障的行和列，包括永久禁用的列和列。 然后可以通过BISR电路重定向这些位置的访问。 然后可以重新执行测试套件，并且如果发现另外的错误，则该设备被认为是有缺陷的。 因此，永远不会启用内存阵列中容易出现故障的行和列。 此外，BIST和BISR电路提供了验证基本内存功能的能力，并在每次应用设备电源时重新映射失败的地址。 存储器阵列的测试覆盖有利地增加。

公开(公告)号：US6137716A

公开(公告)日：2000-10-24

申请号：US920111

申请日：1997-08-26

申请人： Thomas R. Wik

发明人： Thomas R. Wik

IPC分类号： G11C11/406 ,  G11C11/56 ,  G11C16/04

CPC分类号： G11C16/0416 ,  G11C11/5621 ,  G11C11/565 ,  G11C11/412 ,  G11C16/08 ,  G11C7/16 ,  G11C8/14

摘要： A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit includes an array of cells in which each cell has multiple storage elements. At least one of the storage elements performs its function in a different way than the rest of the storage elements. This use of multiple storage mechanisms allows for a greater freedom in memory cell design and allows for the simultaneous storage of multiple states in a single memory cell. Broadly speaking, the present invention contemplates a memory core comprising an address decoder, an array of cells, and a sense amplifier. The address decoder is configured to receive an address and responsively assert a selected word line. The array of cells includes a selected cell coupled to the selected word line, and each cell in the array of cells includes at least two storage elements. A first storage element is configured with a first state which is one of a first plurality of states, and a second storage element is configured with a second state which is one of a second, different plurality of states. The sense amplifier is coupled to the selected cell via a bit line and configured to detect the first and second states. Each cell may further include a third storage element configured with a third state which is one of a third plurality of states. In this case, the sense amplifier is also configured to detect the third state. Examples of candidate storage states include charges on a capacitance, conductivities of transistors, resistances between terminals, turn-on voltages of transistors, currents flowing in closed loops, and orientations of magnetized material.

摘要翻译： 一种在每个存储单元中使用多个存储机制的存储器电路。 在一个实施例中，存储器电路包括其中每个单元具有多个存储元件的单元阵列。 至少一个存储元件以与其余存储元件不同的方式执行其功能。 多个存储机制的使用允许存储器单元设计更大的自由度，并且允许在单个存储器单元中同时存储多个状态。 广义地说，本发明考虑了包括地址解码器，单元阵列和读出放大器的存储器核心。 地址解码器被配置为接收地址并且响应地断言所选择的字线。 单元阵列包括耦合到所选字线的选定单元，并且单元阵列中的每个单元包括至少两个存储元件。 第一存储元件配置有作为第一多个状态之一的第一状态，并且第二存储元件被配置为第二状态，其是第二，不同的多个状态之一。 感测放大器经由位线耦合到所选择的单元并被配置为检测第一和第二状态。 每个单元还可以包括配置有第三状态的第三存储元件，该第三状态是第三多个状态之一。 在这种情况下，读出放大器也被配置为检测第三状态。 候选存储状态的示例包括电容的电荷，晶体管的电导率，端子之间的电阻，晶体管的导通电压，在闭环中流动的电流和磁化材料的取向。

公开(公告)号：US06233197B1

公开(公告)日：2001-05-15

申请号：US09524734

申请日：2000-03-14

申请人： Ghasi R. Agrawal ,  Thomas R. Wik

发明人： Ghasi R. Agrawal ,  Thomas R. Wik

IPC分类号： G11C800

CPC分类号： G11C7/18 ,  G11C8/16

摘要： A multi-port semiconductor memory includes first and second data ports and a plurality of memory cells arranged in rows and columns. Each column comprises first and second pairs of complementary bit lines, which are coupled to each of the memory cells in that column. The first pair of bit lines cross one another between every N and N+1 of the memory cells the column, where N=2M and M is an integer variable greater than zero. A data inversion circuit is coupled between the first pair of bit lines and the first data port, which selectively inverts the first pair of bit lines as a function of the first port's (M+1)th row address input bit only, as measured from the least significant row address input bit.

摘要翻译： 多端口半导体存储器包括第一和第二数据端口以及以行和列排列的多个存储单元。 每列包括第一和第二对互补位线，其被耦合到该列中的每个存储器单元。 第一对位线在存储单元的每个N和N + 1之间彼此交叉，其中N = 2M，M是大于零的整数变量。 数据反相电路耦合在第一对位线与第一数据端口之间，该第一数据端口根据第一端口的第（M + 1）行地址输入位仅选择性地反转第一对位线， 最低有效行地址输入位。

公开(公告)号：US5841695A

公开(公告)日：1998-11-24

申请号：US865470

申请日：1997-05-29

申请人： Thomas R. Wik

发明人： Thomas R. Wik

IPC分类号： G11C11/406 ,  G11C11/56 ,  G11C16/04 ,  G11C16/02

CPC分类号： G11C16/0416 ,  G11C11/5621 ,  G11C11/565 ,  G11C11/412 ,  G11C16/08 ,  G11C7/16 ,  G11C8/14

摘要： A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted. The second gate stores a third charge when the first word line is de-asserted. The data sense module is coupled to the first and second data lines, and configured to sense the second charge if the third word line is asserted while the second word line is asserted. The data sense module is further configured to sense the third charge by detecting a current through the second transistor if the second word line is de-asserted while the third word line is asserted. The data sense module is still further configured to detect the first charge by storing a fourth charge on said second gate if the first word line is asserted while the first data line is de-asserted, the first data line is then asserted, and the first word line is then de-asserted at a predetermined time period after the assertion of the first data line. The fourth charge is then sensed by detecting a current through the second transistor if the second word line is de-asserted while the third word line is asserted. The data sense module determines the state represented by the stored charge quantities. Since additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.