公开(公告)号：US20080046789A1

公开(公告)日：2008-02-21

申请号：US11465864

申请日：2006-08-21

申请人： Igor Arsovski ,  Valerie Chickanosky ,  Rahul Nadkarni ,  Michael Oucllette ,  Reid Wistort

发明人： Igor Arsovski ,  Valerie Chickanosky ,  Rahul Nadkarni ,  Michael Oucllette ,  Reid Wistort

IPC分类号： G01R31/28

CPC分类号： G11C29/50 ,  G11C15/00 ,  G11C29/12 ,  G11C29/12005

摘要： This patent describes a method for varying the amplitude and frequency of power supply oscillations produced by content addressable memories or other critical circuits using BIST. Supply oscillations are produced by performing noisy (high switching activity—high current demand) searches followed by quiet (low switching activity—low current demand) searches. The amplitude and frequency of oscillations can be varied by changing the number of noisy and quiet searches e.g. pattern 1-noisy quiet, noisy, quiet; pattern 2-noisy, noisy, quiet, noisy, noisy, quiet, etc. By going through different patterns the current demand from the CAM macro increases the likelihood of producing worst—case noise and enables testing of CAM operation as well as surrounding circuitry in these noisy conditions.

摘要翻译： 该专利描述了一种用于改变内容可寻址存储器或使用BIST的其他关键电路产生的电源振荡的幅度和频率的方法。 通过执行噪声（高开关活动 - 高电流需求）搜索，然后进行安静（低开关活动 - 低电流需求）搜索来产生供电振荡。 可以通过改变噪声和安静搜索的数量来改变振荡的振幅和频率。 模式1嘈杂安静，嘈杂，安静; 模式2噪声，嘈杂，安静，嘈杂，嘈杂，安静等。通过不同的模式，来自CAM宏的当前需求增加了产生最坏情况噪声的可能性，并且可以测试CAM操作以及周边电路 这些嘈杂的条件。

公开(公告)号：US20050184776A1

公开(公告)日：2005-08-25

申请号：US10708311

申请日：2004-02-24

申请人： Harold Pilo ,  Reid Wistort

发明人： Harold Pilo ,  Reid Wistort

IPC分类号： H03K5/00 ,  H03K5/13 ,  H03L7/06 ,  H03L7/081

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058 ,  H03K2005/00221 ,  H03L7/0818

摘要： A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.

摘要翻译： 用于集成电路器件的延迟锁定环包括与微步延迟链串联的粗延迟链。 粗延迟链包括被配置用于相对于输入时钟信号有选择地提供粗延迟的多个粗延迟单元，并且微步延迟链被配置为选择性地提供关于输入时钟信号的精细延迟调整。 微步延迟链还包括多个并行信号路径，其中一个或多个并行信号路径被电容性加载以提供精细延迟调整。

公开(公告)号：US20050184775A1

公开(公告)日：2005-08-25

申请号：US10708287

申请日：2004-02-23

申请人： Harold Pilo ,  Reid Wistort

发明人： Harold Pilo ,  Reid Wistort

IPC分类号： H03K5/00 ,  H03K5/13 ,  H03L7/06 ,  H03L7/081

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058 ,  H03K2005/00221 ,  H03L7/0818

摘要： A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.