公开(公告)号：US4908683A

公开(公告)日：1990-03-13

申请号：US84556

申请日：1987-08-11

申请人： Dyer A. Matlock ,  Richard L. Lichtel, Jr. ,  Lawrence G. Pearce

发明人： Dyer A. Matlock ,  Richard L. Lichtel, Jr. ,  Lawrence G. Pearce

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/762

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/762 ,  H01L29/66575 ,  Y10S257/90

摘要： The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination. After the polysilicon gate has been delineated, the sloped sidewalls of the field oxide are removed (by anisotropic etching), so that the sidewalls of the apertures or windows of the field oxide layer will be perpendicular to the planar surface of the substrate, thus facilitating proper formation of dielectric (oxide) spacers therealong, which thereby provide separation between contact materials and the junction created by shallow ion implantation of dopants through the field oxide aperture.

摘要翻译： 在直接沟槽晶片处理中使用的沿着场氧化物层的侧壁的不需要的剩余多晶硅桁架的问题通过其中场氧化物层中的孔的侧壁在形成多晶硅层之前初始渐变的处理方案来避免 用于栅极电极。 由于场氧化物层的侧壁的刻度厚度，在其上形成的多晶硅层的厚度在整个衬底上基本均匀。 结果，在随后的多晶硅层的掩模中以限定栅电极的情况下，多晶硅的所有未掩模部分被完全蚀刻，不留下可能是器件污染源的残余材料（例如桁条）。 在描绘多晶硅栅极之后，通过各向异性蚀刻去除场氧化物的倾斜侧壁，使得场氧化物层的孔或窗口的侧壁将垂直于衬底的平面表面，从而便于 在其上正确形成电介质（氧化物）间隔物，从而提供接触材料与通过场氧化物孔径的浅掺杂剂的浅离子注入产生的连接之间的分离。

公开(公告)号：US4814285A

公开(公告)日：1989-03-21

申请号：US19697

申请日：1987-02-27

申请人： Dyer A. Matlock ,  Richard L. Lichtel, Jr.

发明人： Dyer A. Matlock ,  Richard L. Lichtel, Jr.

IPC分类号： H01L21/768 ,  H01L21/283

CPC分类号： H01L21/76879 ,  H01L21/76888

摘要： On the surface of a semiconductor structure containing portions to be selectively connected to an interconnection pattern, a thin conductive, uniform base layer, which promotes the growth of an interconnect conductor, is desposited. To define the interconnect structure, a thick layer of insulation material is selectively formed on the surface of the base layer with openings in the insulation layer exposing portions of the base layer that are to be connected to the interconnect layer. Next, on the portions of the base layer that are exposed by the openings in the insulation layer, a layer of interconnect metal, such as tungsten or gold, that effectively blocks the implantation of the ions through it, is selectively deposited to fill the openings in the insulation layer upon and even with the top surface of the insulation layer, so that the insulation layer and deposited metal are effectively planarized. The base layer which underlies the planarized insulator/interconnect metal layer is selectively converted to an insulator in those regions beneath the insulator but not beneath the interconnect metal by bombarding the entire structure with suitable conversion causing (e.g. oxygen or nitrogen) ions.

摘要翻译： 在包含选择性地连接到互连图案的部分的半导体结构的表面上，导致促进互连导体生长的薄导电均匀的基底层被去除。 为了限定互连结构，在基底层的表面上选择性地形成厚的绝缘材料层，绝缘层中的开口暴露要连接到互连层的基底层的部分。 接下来，在由绝缘层中的开口暴露的基底层的部分上，选择性地沉积有效地阻挡离子注入的诸如钨或金的互连金属层以填充开口 在绝缘层上并且甚至与绝缘层的顶表面之间，使得绝缘层和沉积的金属被有效地平坦化。 在平坦化的绝缘体/互连金属层下面的基底层通过用合适的转换（例如氧或氮）离子轰击整个结构而选择性地转换为绝缘体下方的那些区域中的绝缘体而不是在互连金属下方。

公开(公告)号：US4702000A

公开(公告)日：1987-10-27

申请号：US841297

申请日：1986-03-19

申请人： Dyer A. Matlock ,  Richard L. Lichtel, Jr. ,  Lawrence G. Pearce

发明人： Dyer A. Matlock ,  Richard L. Lichtel, Jr. ,  Lawrence G. Pearce

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/265 ,  H01L21/22

CPC分类号： H01L29/66575 ,  H01L21/28123 ,  H01L21/762 ,  Y10S148/05 ,  Y10S148/086 ,  Y10S148/122 ,  Y10S148/131 ,  Y10S438/978

摘要： The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination. After the polysilicon gate has been delineated, the sloped sidewalls of the field oxide are removed (by anisotropic etching), so that the sidewalls of the apertures or windows of the field oxide layer will be perpendicular to the planar surface of the substrate, thus facilitating proper formation of dielectric (oxide) spacers therealong, which thereby provide separation between contact materials and the junction created by shallow ion implantation of dopants through the field oxide aperture.

公开(公告)号：US4818725A

公开(公告)日：1989-04-04

申请号：US224320

申请日：1988-07-26

申请人： Richard L. Lichtel, Jr. ,  Lawrence G. Pearce ,  Dryer A. Matlock

发明人： Richard L. Lichtel, Jr. ,  Lawrence G. Pearce ,  Dryer A. Matlock

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L29/66583 ,  H01L21/033 ,  H01L21/28123 ,  Y10S148/05 ,  Y10S148/086 ,  Y10S148/122 ,  Y10S148/131

摘要： A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.

摘要翻译： 用于最大化场氧化物层的功能连续性的直接护环晶片处理采用处理顺序，通过该处理顺序在氧化物层中连续地形成各自不同尺寸的孔。 这些孔中的第一个规定了多晶硅栅极的尺寸，而在完成的栅极结构周围形成第二孔径，并且规定了将源极/漏极区域的几何形状引入栅极两侧的衬底的暴露表面区域中。 第一和随后形成的第二孔的侧壁有效地垂直于衬底表面，由此保持场氧化物层在其整体上的功能连续性。 此后，单独的栅极互连层选择性地形成在场氧化物层的顶部，以提供到栅极的导电路径。