公开(公告)号：US20070094623A1

公开(公告)日：2007-04-26

申请号：US11588095

申请日：2006-10-24

申请人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

发明人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

IPC分类号： G06F17/50

CPC分类号： G01R31/31708 ,  G01R31/31704 ,  G01R31/31721 ,  G05B17/02 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5068

摘要： DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

摘要翻译： 提供DFM系统，其通过计算电路设计的绘制布局的互连和器件的形状的预测制造变化来结合集成电路的分析中的制造变化。 互连上的形状变化被转换为电阻 - 电容（RC）寄生效应的变化。 设备上的形状变化将转换为设备参数的变化。 通过确定设备参数和电线寄生变化对标准单元的每个实例的行为的影响，将器件参数和电线寄生效应的变化转换为定时性能，信号完整性和功耗的变化。 这些分析的结果集成到设计流程中，作为增量延迟文件（定时），噪声故障和缓冲区插入/驱动器调整大小命令（噪声）以及漏电功率热点和单元替换命令（功耗）。

公开(公告)号：US08225248B2

公开(公告)日：2012-07-17

申请号：US11588095

申请日：2006-10-24

申请人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

发明人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

IPC分类号： G06F17/50

CPC分类号： G01R31/31708 ,  G01R31/31704 ,  G01R31/31721 ,  G05B17/02 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5068

摘要： DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

摘要翻译： 提供DFM系统，其通过计算电路设计的绘制布局的互连和器件的形状的预测制造变化来结合集成电路的分析中的制造变化。 互连上的形状变化被转换为电阻 - 电容（RC）寄生效应的变化。 设备上的形状变化将转换为设备参数的变化。 通过确定设备参数和电线寄生变化对标准单元的每个实例的行为的影响，将器件参数和电线寄生效应的变化转换为定时性能，信号完整性和功耗的变化。 这些分析的结果集成到设计流程中，作为增量延迟文件（定时），噪声故障和缓冲区插入/驱动器调整大小命令（噪声）以及漏电功率热点和单元替换命令（功耗）。

公开(公告)号：US07673260B2

公开(公告)日：2010-03-02

申请号：US11586827

申请日：2006-10-24

申请人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

发明人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

IPC分类号： G06F17/50

CPC分类号： G01R31/31708 ,  G01R31/31704 ,  G01R31/31721 ,  G05B17/02 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5068

摘要： DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

摘要翻译： 提供DFM系统，其通过计算电路设计的绘制布局的互连和器件的形状的预测制造变化来结合集成电路的分析中的制造变化。 互连上的形状变化被转换为电阻 - 电容（RC）寄生效应的变化。 设备上的形状变化将转换为设备参数的变化。 通过确定设备参数和电线寄生变化对标准单元的每个实例的行为的影响，将器件参数和电线寄生效应的变化转换为定时性能，信号完整性和功耗的变化。 这些分析的结果集成到设计流程中，作为增量延迟文件（定时），噪声故障和缓冲区插入/驱动器调整大小命令（噪声）以及漏电功率热点和单元替换命令（功耗）。

公开(公告)号：US20060128092A1

公开(公告)日：2006-06-15

申请号：US11008007

申请日：2004-12-09

申请人： Richard Rouse

发明人： Richard Rouse

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L29/94 ,  H01L23/481 ,  H01L23/50 ,  H01L29/66189 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the particular circuit device (170) that it is to service. As such, the capacitor (100) and its fabrication process can be optimized in terms of efficiency, etc. The capacitor (100) is fabricated with conductive contacts (162) that allow it to be fused to the device (170) via conductive pads (172) of the device (170). As such, the capacitor (100) and device (170) can be packaged together and valuable semiconductor real estate can be conserved as the capacitor (100) is not formed out of the same substrate as the device (170). The capacitor (100) further includes deep contacts (150, 152) whereon bond pads (180, 182) can be formed that allow electrical connection of the capacitor (100) and device (170) to the outside world.

公开(公告)号：US20190210283A1

公开(公告)日：2019-07-11

申请号：US15901889

申请日：2018-02-22

申请人： Richard Rouse

发明人： Richard Rouse

IPC分类号： B29C64/227 ,  B33Y30/00 ,  B33Y50/02 ,  B29C64/209 ,  B29C64/393

CPC分类号： B29C64/227 ,  B29C64/209 ,  B29C64/393 ,  B33Y30/00 ,  B33Y50/02

摘要： Enclosed is a description of a high throughput 3D printing and imaging system that can be used for multiple laboratory purposes from bioassay fabrication to analysis. This compact system is designed to work with multiple microwell plates and slides. It also contains linear encoders for precise positional control in the XYZ direction. A syringe pump and 3 way select valve configuration and interrelated microfluidics are described and compact stepper motor driven linear actuators for moving tools on the gantry head is also explained. In addition, there is a visualization and sorting area for measuring droplets and for deflecting charged particles magnetized collection tubes. There is also an imaging module for quantifying fluorescence abundance and an analog signal triggered camera that can be synchronized with dispensers that can be used for synchronized imaging and data collection.

公开(公告)号：US20070099314A1

公开(公告)日：2007-05-03

申请号：US11586827

申请日：2006-10-24

申请人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

发明人： Haizhou Chen ,  Li-Fu Chang ,  Richard Rouse ,  Nishath Verghese

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R31/31708 ,  G01R31/31704 ,  G01R31/31721 ,  G05B17/02 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5068

摘要： DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

摘要翻译： 提供DFM系统，其通过计算电路设计的绘制布局的互连和器件的形状的预测制造变化来结合集成电路的分析中的制造变化。 互连上的形状变化被转换为电阻 - 电容（RC）寄生效应的变化。 设备上的形状变化将转换为设备参数的变化。 通过确定设备参数和电线寄生变化对标准单元的每个实例的行为的影响，将器件参数和电线寄生效应的变化转换为定时性能，信号完整性和功耗的变化。 这些分析的结果集成到设计流程中，作为增量延迟文件（定时），噪声故障和缓冲区插入/驱动器调整大小命令（噪声）以及漏电功率热点和单元替换命令（功耗）。

公开(公告)号：US20060065946A1

公开(公告)日：2006-03-30

申请号：US10954926

申请日：2004-09-30

申请人： Freidoon Mehrad ,  Richard Rouse ,  Robert Churchill

发明人： Freidoon Mehrad ,  Richard Rouse ,  Robert Churchill

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a multi-doped semiconductor e-fuse for use in an integrated circuit and a method of manufacture therefore. In one aspect, the semiconductor e-fuse 200 includes a semiconductor body 205 having a neck region 220 interposed a first portion 210 of the semiconductor body 205 and a second portion 215 of the semiconductor body 205. The semiconductor body 205 is doped with opposite type dopants, and a conductive layer 230 is located over and extends across the neck region 220 to electrically connect the first portion 210 with the second portion 215.

摘要翻译： 本发明提供一种用于集成电路的多掺杂半导体电子熔断器及其制造方法。 在一个方面，半导体电子熔丝200包括半导体本体205，半导体本体205具有插入半导体本体205的第一部分210的颈部区域220和半导体本体205的第二部分215。 半导体主体205被掺杂有相反类型的掺杂剂，并且导电层230位于颈部区域220之上并延伸穿过颈部区域220以将第一部分210与第二部分215电连接。

公开(公告)号：US6080630A

公开(公告)日：2000-06-27

申请号：US243014

申请日：1999-02-03

申请人： Ognjen Milic-Strkalj ,  Richard Rouse ,  Zoran Krivokapic

发明人： Ognjen Milic-Strkalj ,  Richard Rouse ,  Zoran Krivokapic

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/10

CPC分类号： H01L29/6659 ,  H01L21/2253 ,  H01L29/1045

摘要： The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface of the semiconductor substrate, and a polysilicon gate is formed on the surface of the gate oxide. A first implant of a dopant of the first conductivity type is performed so as to form self-compensating implant regions in the semiconductor substrate on opposite sides of the gate. Disposable sidewall spacers are then formed around the polysilicon gate. A second implant of a dopant of a second conductivity type is performed so as to create highly-doped source/drain regions which are self-aligned to the sidewall spacers. The substrate with self-compensating implant regions and the highly-doped source/drain regions is then subject to a rapid thermal anneal (RTA) process so as to activate the dopant in the self-compensating implant regions and the highly-doped source/drain regions. The dopant within the self-compensating regions diffuses laterally under the polysilicon gate to define pockets. Thereafter, the disposable sidewall spacers are removed. Finally, a third implant of a dopant of the second conductivity type is performed so as to create lightly-doped source/drain regions in the self-compensating implant regions on opposite sides of the gate.

摘要翻译： 本发明提供一种用于形成具有自补偿阈值调整植入物和降低结电容的MOS器件的方法。 提供第一导电类型的半导体衬底。 在半导体衬底的表面上形成栅极氧化物，并且在栅极氧化物的表面上形成多晶硅栅极。 执行第一导电类型的掺杂剂的第一注入，以在栅极的相对侧上的半导体衬底中形成自补偿注入区域。 然后在多晶硅栅极周围形成一次性侧壁间隔物。 执行第二导电类型的掺杂剂的第二注入，以便产生与侧壁间隔物自对准的高掺杂源/漏区。 然后，具有自补偿注入区域和高掺杂源极/漏极区域的衬底经受快速热退火（RTA）工艺，以激活自补偿注入区域中的掺杂剂和高掺杂源极/漏极 地区。 自补偿区域内的掺杂剂在多晶硅栅极下方横向扩散以形成凹穴。 此后，去除一次性侧壁间隔物。 最后，执行第二导电类型的掺杂剂的第三注入，以在栅极的相对侧上的自补偿注入区域中产生轻掺杂的源极/漏极区域。

公开(公告)号：US06242329B1

公开(公告)日：2001-06-05

申请号：US09243875

申请日：1999-02-03

申请人： Carl Robert Huster ,  Concetta Riccobene ,  Richard Rouse ,  Donald L. Wollesen

发明人： Carl Robert Huster ,  Concetta Riccobene ,  Richard Rouse ,  Donald L. Wollesen

IPC分类号： H01L21425

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/045 ,  H01L29/1045 ,  H01L29/6656

摘要： A method for manufacturing a field effect transistor (100) includes steps of forming a gate stack (102) on the surface (114) of a semiconductor substrate (108), and defining source/drain regions (104, 106) on either side of the gate stack and a channel region (130) under the gate stack. The channel region has one end (132) proximate a first source/drain region and another end (134) proximate a second source/drain region. The method further includes forming a masking layer (174) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

摘要翻译： 一种用于制造场效应晶体管（100）的方法包括以下步骤：在半导体衬底（108）的表面（114）上形成栅叠层（102），并且在半导体衬底（108）的任一侧上限定源/漏区（104,106） 栅极堆叠和栅极堆叠下方的沟道区域（130）。 沟道区域具有靠近第一源极/漏极区域的一个端部（132）和靠近第二源极/漏极区域的另一端部（134）。 该方法还包括在半导体衬底的表面上形成掩模层（174）。 掩模层具有标称对准位置和不对准公差。 该方法还包括在半导体衬底中注入掺杂离子以不对称地掺杂场效应晶体管，包括选择足够的倾斜角和旋转角（B，D，F，H），以确保通道区域的一端的阴影 注入掺杂离子。