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公开(公告)号：US08806227B2
公开(公告)日：2014-08-12
申请号：US11620794
申请日：2007-01-08
CPC分类号： G06F21/6218
摘要： A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.
摘要翻译： 一种通过产生随机化值来存储敏感数据的方法，将敏感数据和随机化值变换为结果，并将结果的分离部分存储在至少两个存储设备上，使得如果敏感数据中的任何一个 存储设备受到损害。
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公开(公告)号：US07373629B2
公开(公告)日：2008-05-13
申请号：US11113615
申请日：2005-04-25
CPC分类号： H01L27/11898 , H01L27/0207
摘要： An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.
摘要翻译： 一种包括集成电路的装置，其具有（i）多个区域，每个区域预扩散并被配置为金属编程;以及（ii）多个引脚，被配置为将集成电路连接到插座。 逻辑部分可以在被配置为实现集成电路操作的集成电路（i）上实现，并且（ii）具有一个或多个I / O连接和一个或多个供电连接。 预扩散区域的第一组被金属编程并耦合到所述I / O连接。 第二组预扩散区域是金属编程的，并且耦合到电源连接。
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3.发明授权Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an I/O region 失效用于多槽金属掩模可编程可重定位功能的互连方法放置在I / O区域中公开(公告)号：US07292063B2
公开(公告)日：2007-11-06
申请号：US11120067
申请日：2005-05-02
CPC分类号： H01L27/11898 , G06F17/5077 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.
摘要翻译： 一种用于互连金属掩模可编程功能的子功能的方法，其包括以下步骤：（A）形成平台应用专用集成电路（ASIC）的基层，所述平台专用集成电路（ASIC）包括围绕所述平台周围设置的多个预扩散区域 ASIC，（B）形成功能的两个或更多个子功能，其中金属掩模集放置在平台应用专用集成电路的多个预扩散区域的数量上，以及（C）配置一个或多个连接点 两个或更多个子功能中的每一个，使得两个或多个子功能之间的互连是可在单个层中可路由的工具。 每个预扩散区域被配置为金属可编程的。
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公开(公告)号：US5754080A
公开(公告)日：1998-05-19
申请号：US834154
申请日：1997-04-14
申请人： Dao-Long Chen , Robert D. Waldron
发明人： Dao-Long Chen , Robert D. Waldron
CPC分类号： H03D13/002 , H03L7/0891
摘要： A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.
摘要翻译： 单边沿触发相位检测器，提供高速相位检测。 相位检测器仅工作在时钟和数据信号的单个边沿，可以是上升沿或下降沿。 提取的控制信号被锁存至少一个时钟周期的一半或更多，以确保完整的轨至轨摆动。
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5.发明授权
公开(公告)号：US5726991A
公开(公告)日：1998-03-10
申请号：US545915
申请日：1995-10-20
摘要： A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.
摘要翻译： 一种数据通信方法和装置，包括一个积分误码率测试系统。 该系统适于接收要通过通信链路传输的数字数据信号，并且包括用于将数据信号发送到链路上的发射机。 测试信号模式发生器产生数字比特测试信号的可确定模式，其可插入到发射机的输入端代替数字数据信号。 接收机耦合到链路以用于接收比特测试信号，并将比特测试信号的接收模式与可确定模式进行比较。 误码率是根据发送的测试信号与可确定模式之间的比特差数来计算的。
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公开(公告)号：US5363066A
公开(公告)日：1994-11-08
申请号：US78880
申请日：1993-06-16
申请人： Dao-Long Chen , Robert D. Waldron
发明人： Dao-Long Chen , Robert D. Waldron
CPC分类号： H03L7/0898 , H03L7/0896
摘要： A charge pump circuit for a phase-locked loop circuit which provides substantially constant charge and discharge currents characterized by minimal overshoots and undershoots. The charge pump circuit includes a level shifter circuit which attenuates voltage swings in Up and Down signals from the phase detector and provides control signals. The charge pump circuit also includes a feedback circuit coupled to the level shifter which compares the output voltage of the charge pump to predetermined first and second reference voltages and increases and decreases the charge and discharge currents to minimize overshoot and undershoot noise as determined by the control signals.
摘要翻译： 用于锁相环电路的电荷泵电路，其提供基本上恒定的充电和放电电流，其特征在于最小的过冲和下冲。 电荷泵电路包括电平移位器电路，其衰减来自相位检测器的向上和向下信号中的电压摆幅并提供控制信号。 电荷泵电路还包括耦合到电平转换器的反馈电路，其将电荷泵的输出电压与预定的第一和第二参考电压进行比较，并且增加和减少充电和放电电流，以最小化由控制器确定的过冲和下冲噪声 信号。
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公开(公告)号：US4014706A
公开(公告)日：1977-03-29
申请号：US569834
申请日：1975-04-21
申请人： Robert D. Waldron
发明人： Robert D. Waldron
IPC分类号： C04B35/486 , C04B35/50 , C04B35/00 , C04B35/48
CPC分类号： C04B35/50 , C04B35/486
摘要： New compositions of matter each consisting essentially of a solid solution of compounds and a halide binder aid. The novel compositions have melting points above 1800.degree. C, high mechanical integrity, low thermal conductivity, and are essentially non-reactive with molten reactive and refractory metals. The novel compositions sinter at 1000.degree. to 1300.degree. C.
摘要翻译： 各种新的组合物，主要由化合物和卤化物粘合剂的固溶体组成。 该新型组合物具有高于1800℃的熔点，高机械完整性，低导热性，并且基本上与熔融的反应性和难熔金属无反应性。 该新型组合物在1000℃至1300℃下烧结
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公开(公告)号：US3597022A
公开(公告)日：1971-08-03
申请号：US3597022D
申请日：1969-07-22
申请人： ROBERT D WALDRON
发明人： WALDRON ROBERT D
IPC分类号： F16C39/06
CPC分类号： F16C39/063 , F16C32/0436
摘要： Diamagnetic levitation and/or stabilizing devices, wherein diamagnetic members are levitated in relation to permanent magnets. Said magnets in repulsion levitation relative to each other are stabilized along one or more desired axes by means of diamagnetic members disposed about said axes, and in relation to fields of permanent magnets.
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9.发明授权Use of configurable mixed-signal building block functions to accomplish custom functions 有权使用可配置的混合信号构建块功能来完成自定义功能公开(公告)号：US07478354B2
公开(公告)日：2009-01-13
申请号：US11133815
申请日：2005-05-20
IPC分类号： G06F17/50
CPC分类号： H01L27/118 , G06F17/5068 , H01L27/0207 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.
摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括在第一制造阶段期间仅制造直到并包括第一金属层的芯片，使得芯片的输入/输出（I / O）区域具有多个槽，其中， 槽具有多个第一晶体管。 该方法的第二步可以包括响应于在第一制造开始之后创建的定制设计来设计在第一金属层上方的多个上金属层，上金属层将多个第一晶体管互连以形成多个 混合信号构建块功能。 该方法的第三步可以涉及制造芯片以在第二制造阶段添加上金属层。
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公开(公告)号：US07360178B2
公开(公告)日：2008-04-15
申请号：US11136180
申请日：2005-05-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.
摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括仅制造直到并包括第一金属层的芯片，使得芯片的芯区域具有单元阵列，每个单元具有多个晶体管。 第二步通常包括响应于在第一制造开始之后产生的定制设计而在第一金属层之上设计多个上金属层，上金属层互连多个单元以形成（i）混合信号 模块和（ii）数字模块，所述混合信号模块产生至少一个模拟信号和至少一个数字信号。 在第三步骤中，该方法可以包括制造芯片以添加上部金属层。
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