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    Capacitive sensor, integrated circuit, electronic device and method
    2.
    发明授权
    Capacitive sensor, integrated circuit, electronic device and method 有权
    电容式传感器，集成电路，电子设备及方法

    公开(公告)号：US08779781B2

    公开(公告)日：2014-07-15

    申请号：US13438716

    申请日：2012-04-03

    申请人： Viet Hoang Nguyen ,  Roel Daamen ,  Axel Nackaerts ,  Pascal Bancken

    发明人： Viet Hoang Nguyen ,  Roel Daamen ,  Axel Nackaerts ,  Pascal Bancken

    IPC分类号： G01R27/26

    CPC分类号： G01N27/223 ,  G01N27/226

    摘要： A sensor for sensing an analyte includes capacitive elements, each having a pair of electrodes separated by a dielectric wherein the dielectric constant of the dielectric of at least one of the capacitive elements is sensitive to the analyte, the sensor further including a comparator adapted to compare a selected set of capacitive elements against a reference signal and to generate a comparison result signal, and a controller for iteratively selecting the set in response to the comparison result signal, wherein the sensor is arranged to produce a digitized output signal indicative of the sensed level of the analyte of interest. An IC comprising such a sensor, an electronic device comprising such an IC and a method of determining a level of an analyte of interest using such a sensor are also disclosed.

    摘要翻译： 用于感测分析物的传感器包括电容元件，每个电容元件具有由电介质隔开的一对电极，其中至少一个电容元件的电介质的介电常数对分析物敏感，所述传感器还包括比较器， 相对于参考信号选择的一组电容性元件并产生比较结果信号;以及控制器，用于响应于所述比较结果信号迭代地选择所述集合，其中所述传感器被布置成产生指示感测电平的数字化输出信号 的感兴趣的分析物。 还公开了一种包括这种传感器的IC，包括这种IC的电子设备以及使用这种传感器确定感兴趣分析物的水平的方法。

    INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR
    3.
    发明申请
    INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR 有权
    集成电路及其制造方法

    公开(公告)号：US20110296912A1

    公开(公告)日：2011-12-08

    申请号：US12962460

    申请日：2010-12-07

    申请人： Matthias Merz ,  Roel Daamen ,  Aurelie Humbert ,  Youri Victorovitch Ponomarev

    发明人： Matthias Merz ,  Roel Daamen ,  Aurelie Humbert ,  Youri Victorovitch Ponomarev

    IPC分类号： G01N27/12 ,  H01L21/28

    CPC分类号： G01N27/121 ,  G01M3/045 ,  G01N27/06

    摘要： Disclosed is an integrated circuit comprising an electrode arrangement for detecting the presence of a liquid, said electrode arrangement comprising a first electrode and a second electrode, wherein, prior to exposure of the electrode arrangement to said liquid, a surface of at least one of the first electrode and second electrode is at least partially covered by a compound that is soluble in the liquid; the electrical properties of the electrode arrangement being dependent on the amount of the compound covering said surface. An package and electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.

    摘要翻译： 公开了一种集成电路，其包括用于检测液体存在的电极装置，所述电极装置包括第一电极和第二电极，其中在将电极装置暴露于所述液体之前，至少一个 第一电极和第二电极至少部分被可溶于液体的化合物覆盖; 电极布置的电性能取决于覆盖所述表面的化合物的量。 还公开了包括这种IC的封装和电子器件以及制造这种IC的方法。

    FOOD PACKAGE WITH INTEGRATED RFID-TAG AND SENSOR
    4.
    发明申请
    FOOD PACKAGE WITH INTEGRATED RFID-TAG AND SENSOR 有权
    具有集成RFID标签和传感器的食品包装

    公开(公告)号：US20110291806A1

    公开(公告)日：2011-12-01

    申请号：US13116920

    申请日：2011-05-26

    申请人： Romano Hoofman ,  Roel Daamen ,  Youri Victorovitch Ponomarev ,  Fotopoulou Kyriaki ,  Matthias Merz ,  Gilberto Curatola ,  Anton Tombeur

    发明人： Romano Hoofman ,  Roel Daamen ,  Youri Victorovitch Ponomarev ,  Fotopoulou Kyriaki ,  Matthias Merz ,  Gilberto Curatola ,  Anton Tombeur

    IPC分类号： H04Q5/22

    CPC分类号： B65D79/02 ,  B65D2203/10 ,  G01N33/0062 ,  G01N33/02

    摘要： A container for containing a perishable substance has a container wall with an inner side and an outer side. The wall has an electrically conductive layer extending between the inner side and the outer side. The inner side faces the space containing the substance. The container comprises electronic circuitry having a sensor for sensing a physical property or condition of the substance, and an antenna for communicating an RF signal to a receiver, external to the container. The RF signal is indicative of the physical property or condition sensed. The sensor is positioned so as to be exposed to the space containing the substance in operational use of the container. The antenna is positioned at the outer side, or between the outer side and the electrically conductive layer, and is electrically isolated from the electrically conductive layer.

    摘要翻译： 用于容纳易腐物质的容器具有容纳有内侧和外侧的容器壁。 该壁具有在内侧和外侧之间延伸的导电层。 内侧面向包含物质的空间。 容器包括具有用于感测物质的物理性质或状况的传感器的电子电路和用于将RF信号传送到容器外部的接收器的天线。 RF信号表示所感测到的物理属性或状况。 传感器被定位成在容器的操作使用中暴露于容纳物质的空间。 天线位于外侧，或位于外侧和导电层之间，并且与导电层电隔离。

    INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR
    5.
    发明申请
    INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR 有权
    集成电路及其制造方法

    公开(公告)号：US20110018097A1

    公开(公告)日：2011-01-27

    申请号：US12843809

    申请日：2010-07-26

    申请人： Youri Ponomarev ,  Aurelie Humbert ,  Roel Daamen

    发明人： Youri Ponomarev ,  Aurelie Humbert ,  Roel Daamen

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L23/3107 ,  G01N27/128 ,  G01N27/223 ,  H01L23/291 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Disclosed is an integrated circuit (IC) comprising a substrate (10) including a plurality of circuit elements and a metallization stack (20) covering said substrate for providing interconnections between the circuit elements, wherein the top metallization layer of said stack carries a plurality of metal portions (30) embedded in an exposed porous material (40) for retaining a liquid, said porous material laterally separating said plurality of metal portions. An electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.

    摘要翻译： 公开了一种集成电路（IC），其包括包括多个电路元件的基板（10）和覆盖所述基板的金属化叠层（20），用于提供电路元件之间的互连，其中所述堆叠的顶部金属化层承载多个 嵌入暴露的多孔材料（40）中用于保持液体的金属部分（30），所述多孔材料横向分离所述多个金属部分。 还公开了包括这种IC的电子设备和制造这种IC的方法。

    Method of forming an interconnect structure
    6.
    发明授权
    Method of forming an interconnect structure 有权
    形成互连结构的方法

    公开(公告)号：US07790606B2

    公开(公告)日：2010-09-07

    申请号：US12444677

    申请日：2007-10-05

    申请人： Roel Daamen

    发明人： Roel Daamen

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L2221/1031

    摘要： A method of forming an interconnect structure in a semiconductor device in which via holes (62) defined in a dielectric layer are filled with a filler material (64), such as a porogen material, before a further dielectric layer (66) is deposited thereover. Trenches (72) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.

    摘要翻译： 在半导体器件中形成互连结构的方法，其中在介质层（62）中限定的通孔（62）填充有诸如致孔剂材料的填充材料（64），之后在其上沉积另外的电介质层（66） 。 沟槽（72）形成在另外的电介质层中，然后去除在通孔中暴露的填充材料。 该方法提供了一个强大的过程，它提供改进的通孔和沟槽轮廓控制。

    Polishing apparatus and two-step method of polishing a metal layer of an integrated circuit
    7.
    发明授权
    Polishing apparatus and two-step method of polishing a metal layer of an integrated circuit 失效
    抛光装置和两步法抛光集成电路的金属层

    公开(公告)号：US07709387B2

    公开(公告)日：2010-05-04

    申请号：US10544411

    申请日：2004-01-23

    申请人： Viet Nguyen Hoang ,  Roel Daamen

    发明人： Viet Nguyen Hoang ,  Roel Daamen

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by polishing for a first period of time, after which an etching agent (25) is added to the polishing liquid (24) and polishing is continued for a second period of time for removing portions of the metal (15) remaining outside the opening (13). The polishing apparatus (40) is able to perform the method.

    摘要翻译： 根据本发明的制造集成电路（IC）的方法开始于提供一种包括电气装置（2）并具有涂覆有电介质材料（12）的表面（11）的预制集成电路（10）和 金属（15）。 可以通过阻挡层（14）与金属（15）分离的电介质材料（12）具有填充有金属（15）的开口（13）。 通过在第一时间内抛光除去开口（13）外部的金属部分（15），然后将蚀刻剂（25）加入到抛光液体（24）中，继续研磨第二周期 用于去除剩余在开口（13）外部的金属（15）的部分的时间。 抛光装置（40）能够执行该方法。

    Method of manufacturing a semiconductor device having damascene structures with air gaps
    8.
    发明申请
    Method of manufacturing a semiconductor device having damascene structures with air gaps 有权
    制造具有气隙的镶嵌结构的半导体器件的方法

    公开(公告)号：US20050221600A1

    公开(公告)日：2005-10-06

    申请号：US11084081

    申请日：2005-03-17

    申请人： Roel Daamen ,  Greja Johanna Verheijden

    发明人： Roel Daamen ,  Greja Johanna Verheijden

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.

    摘要翻译： 提供一种制造具有气隙的镶嵌结构的半导体器件的方法。 在一个实施例中，该方法包括提供具有第一金属层的基本上平坦的层，沉积通孔层介电层，图案化通孔层电介质层，至少部分刻蚀通孔层电介质层，至少在至少 图案化一次性层，沉积第二金属层，平面化第二金属层，在平坦化第二金属层之后沉积可渗透介电层，以及通过可渗透介电层去除一次性层以形成气隙。