公开(公告)号：US07679984B2

公开(公告)日：2010-03-16

申请号：US11695676

申请日：2007-04-03

申请人： Rom-Shen Kao

发明人： Rom-Shen Kao

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C2207/105

摘要： A data path in a memory device is configured by selecting a data path configuration configured to at least partially maintain data bit order between the memory device and a chip carrier. The memory data path is arranged based on the data path configuration for memory operations where maintaining data bit order between the memory device and the chip carrier is required.

摘要翻译： 通过选择被配置为至少部分地维持存储器件和芯片载体之间的数据位顺序的数据路径配置来配置存储器件中的数据路径。 存储器数据路径基于用于在存储器件和芯片载体之间保持数据位顺序的存储器操作的数据路径配置被布置。

公开(公告)号：US5774648A

公开(公告)日：1998-06-30

申请号：US725685

申请日：1996-10-02

申请人： Rom-Shen Kao ,  Vickie L. Gibbs

发明人： Rom-Shen Kao ,  Vickie L. Gibbs

IPC分类号： G06F12/16 ,  G06F3/06 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  G06F11/10

CPC分类号： H03M13/151 ,  G11B20/1833

摘要： An address generator provided on an error control chip of an optical disk storage for addressing a plurality of working buffers accessed by a CPU, an optical disk drive (ODD), and encoder/decoder circuitry during error correction operations. The address generator comprises a loading address generator that produces an adop address signal to provide linear buffer access for the CPU and ODD when data are supplied from and to the CPU and ODD for encoding and decoding. A processing address generator produces an adex address signal that provides interleaving and random buffer access for the encoder/decoder circuitry during data encoding and decoding operations. A buffer rotation control circuit produces address and data bus control signals to provide the rotation of the buffers between the CPU, ODD, and encoder/decoder circuitry in various encoding and decoding cycles to support a pipeline error control arrangement.

摘要翻译： 提供在光盘存储器的错误控制芯片上的地址发生器，用于在纠错操作期间寻址由CPU访问的多个工作缓冲器，光盘驱动器（ODD）和编码器/解码器电路。 地址生成器包括一个加载地址生成器，该数据产生一个adop地址信号，以便在从CPU提供数据和向编码和解码的ODD提供数据时，为CPU和ODD提供线性缓冲区访问。 处理地址发生器产生一个adex地址信号，该数据在数据编码和解码操作期间为编码器/解码器电路提供交织和随机缓冲器访问。 缓冲器旋转控制电路产生地址和数据总线控制信号，以在各种编码和解码周期中在CPU，ODD和编码器/解码器电路之间提供缓冲器的旋转，以支持流水线错误控制装置。

公开(公告)号：US07822910B2

公开(公告)日：2010-10-26

申请号：US11843550

申请日：2007-08-22

申请人： Rom-Shen Kao

发明人： Rom-Shen Kao

IPC分类号： G06F12/06 ,  G11C8/10

CPC分类号： G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C29/76

摘要： Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

摘要翻译： 本发明的实施例通常可以提供允许将多芯片封装（MCP）中的存储器件映射到地址空间的存储器段的技术。 对于一些实施例，对于每个存储器设备加载对应于该设备被映射到的存储器段的多位设备ID。 然后将较高阶地址位与分配给每个器件的器件ID进行比较。 对于具有地址位和其器件ID之间匹配的器件，内部生成的片选线被断言。

公开(公告)号：US20080007569A1

公开(公告)日：2008-01-10

申请号：US11456061

申请日：2006-07-06

申请人： Rom-Shen Kao

发明人： Rom-Shen Kao

IPC分类号： G09G5/00

CPC分类号： G06F12/1027

摘要： Embodiments of the invention generally provide a method for configuring an overlay window in a volatile memory device. In one embodiment, the method includes receiving a first command which provides at least a portion of a base address for the overlay window, wherein the overlay window comprises a range of memory addresses, and receiving a second command which provides a size of the overlay window. An access command received by the volatile memory device is used to access a memory array of the volatile memory device if an address of the access command is outside of the overlay window. The access command received by the volatile memory device is used to access a memory location outside of the memory array if the address of the access command is within the overlay window.

摘要翻译： 本发明的实施例通常提供一种用于在易失性存储器件中配置覆盖窗口的方法。 在一个实施例中，该方法包括接收提供覆盖窗口的基地址的至少一部分的第一命令，其中覆盖窗口包括一定范围的存储器地址，以及接收提供覆盖窗口大小的第二命令 。 如果访问命令的地址在覆盖窗口之外，则由易失性存储器件接收的访问命令用于访问易失性存储器设备的存储器阵列。 如果访问命令的地址在覆盖窗口内，则由易失性存储器件接收的访问命令用于访问存储器阵列外的存储器位置。

公开(公告)号：US20070230266A1

公开(公告)日：2007-10-04

申请号：US11397429

申请日：2006-04-04

申请人： Rom-Shen Kao

发明人： Rom-Shen Kao

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4093

摘要： One embodiment of the invention provides a method for reading data. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data received at a corresponding time, and detecting a first time region during which the data is received. The method also includes using the detected first time region to determine a second time region during which the data may be read using the second clock signal and reading the data using a second clock signal during the second time region.

摘要翻译： 本发明的一个实施例提供了一种读取数据的方法。 该方法包括从使用每个产生的脉冲来锁存在相应时间接收到的数据的第一时钟信号产生两个或更多个脉冲，通过该第一时钟信号接收要读取的数据，并且检测接收数据的第一时间区域。 该方法还包括使用检测到的第一时间区域来确定可以使用第二时钟信号读取数据并在第二时间区域期间使用第二时钟信号读取数据的第二时间区域。

公开(公告)号：US07899961B2

公开(公告)日：2011-03-01

申请号：US12202485

申请日：2008-09-02

申请人： Rom-Shen Kao

发明人： Rom-Shen Kao

IPC分类号： G06F13/00

CPC分类号： G06F13/4072 ,  G11C7/1006

摘要： In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.

摘要翻译： 在一个实施例中，集成电路包括用于执行总线反转的电路。 电路可操作以配置集成电路以实现集成电路能够执行的多个总线反转方案之一。 该电路还可操作用于基于集成电路配置的总线反演方案来处理输入到集成电路和从集成电路输出的数据。

公开(公告)号：US07843753B2

公开(公告)日：2010-11-30

申请号：US12051387

申请日：2008-03-19

申请人： Peter Mayer ,  Nicholas Heath ,  Rom-Shen Kao ,  Jason Parrish

发明人： Peter Mayer ,  Nicholas Heath ,  Rom-Shen Kao ,  Jason Parrish

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40626

摘要： An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.

摘要翻译： 集成电路包括存储单元阵列和第一电路。 阵列包括字线。 每个字线耦合到多个存储单元。 第一电路被配置为响应于刷新命令来沿着第一数量的字线刷新存储器单元。 字线的第一数量是基于检测到的温度。

公开(公告)号：US20100057971A1

公开(公告)日：2010-03-04

申请号：US12202485

申请日：2008-09-02

申请人： Rom-Shen Kao

发明人： Rom-Shen Kao

IPC分类号： G06F13/00

CPC分类号： G06F13/4072 ,  G11C7/1006

摘要： In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.

摘要翻译： 在一个实施例中，集成电路包括用于执行总线反转的电路。 电路可操作以配置集成电路以实现集成电路能够执行的多个总线反转方案之一。 该电路还可操作用于基于集成电路配置的总线反演方案来处理输入到集成电路和从集成电路输出的数据。

公开(公告)号：US20090052267A1

公开(公告)日：2009-02-26

申请号：US11843558

申请日：2007-08-22

申请人： ROM-SHEN KAO

发明人： ROM-SHEN KAO

IPC分类号： G11C8/00

CPC分类号： G11C8/06 ,  G11C5/02 ,  G11C5/04 ,  G11C5/066 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2924/01055 ,  H01L2924/00014

摘要： Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

摘要翻译： 本发明的实施例通常可以提供允许单个外部供应的芯片选择信号用于独立地选择多芯片封装（MCP）中的多个器件的技术。 对于一些实施例，将较高阶地址位与分配给每个设备的设备ID进行比较。 对于具有地址位和其器件ID之间匹配的器件，内部生成的片选线被断言。

公开(公告)号：US07451263B2

公开(公告)日：2008-11-11

申请号：US11349631

申请日：2006-02-08

申请人： Jong-Hoon Oh ,  Rom-Shen Kao

发明人： Jong-Hoon Oh ,  Rom-Shen Kao

IPC分类号： G06F13/14

CPC分类号： G06F13/1694 ,  Y02D10/14

摘要： Embodiments of the invention provide a method and apparatus for accessing a non-volatile memory controller and a volatile memory via a shared interface. In one embodiment, the method includes selecting one of the non-volatile memory controller and the volatile memory via shared control signals of the shared interface, wherein the shared control signals are issued to the non-volatile memory controller and the volatile memory. The method also includes issuing commands to the selected one of the non-volatile memory controller and the volatile memory via the shared control signals.

摘要翻译： 本发明的实施例提供了一种用于经由共享接口访问非易失性存储器控制器和易失性存储器的方法和装置。 在一个实施例中，该方法包括通过共享接口的共享控制信号选择非易失性存储器控制器和易失性存储器之一，其中共享控制信号被发布到非易失性存储器控制器和易失性存储器。 该方法还包括通过共享控制信号向非易失性存储器控制器和易失性存储器中选定的一个发出命令。