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公开(公告)号：US08868992B2
公开(公告)日：2014-10-21
申请号：US12651252
申请日：2009-12-31
申请人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
发明人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译： 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。
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公开(公告)号：US20150278058A1
公开(公告)日：2015-10-01
申请号：US14231240
申请日：2014-03-31
申请人： TSVIKA KURTS , EILON HAZAN , SEAN T. BAARTMANS , MARCUS R. WINSTON , RONY GHATTAS , ARIE BERNSTEIN , TODD M. WITTER , MARCELO YUFFE
发明人： TSVIKA KURTS , EILON HAZAN , SEAN T. BAARTMANS , MARCUS R. WINSTON , RONY GHATTAS , ARIE BERNSTEIN , TODD M. WITTER , MARCELO YUFFE
CPC分类号： G06F11/3476 , G06F11/3024 , G06F11/323 , G06F11/3409 , G06F11/3466 , G06F11/3636 , G06F11/3656
摘要： A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.
摘要翻译： 处理设备包括调试端口控制器，用于监视处理设备的操作，以确定处理设备是否以第一模式或第二模式操作，并且收集包括处理设备的操作特性的跟踪信息。 处理装置还包括显示引擎逻辑，用于处理显示数据以输出到显示装置。 此外，处理装置包括显示引擎接口，用于当处理装置以第一主模式操作时，向多个现有平台连接器提供来自显示引擎逻辑的显示数据，以及来自调试端口控制器的跟踪信息 当处理装置以由调试端口控制器确定的第二模式操作时。
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公开(公告)号：US20110161752A1
公开(公告)日：2011-06-30
申请号：US12651252
申请日：2009-12-31
申请人： BRYAN L. SPRY , THEODORE Z. SCHOENBORN , PHILIP ABRAHAM , CHRISTOPHER P. MOZAK , DAVID G. ELLIS , JAY J. NEJEDLO , BRUCE QUERBACH , ZVIKA GREENFIELD , RONY GHATTAS , JAYASEKHAR THOLIYIL , CHARLES D. LUCAS , CHRISTOPHER E. YUNKER
发明人： BRYAN L. SPRY , THEODORE Z. SCHOENBORN , PHILIP ABRAHAM , CHRISTOPHER P. MOZAK , DAVID G. ELLIS , JAY J. NEJEDLO , BRUCE QUERBACH , ZVIKA GREENFIELD , RONY GHATTAS , JAYASEKHAR THOLIYIL , CHARLES D. LUCAS , CHRISTOPHER E. YUNKER
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译： 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。
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