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    TRAINING FOR MAPPING SWIZZLED DATA TO COMMAND/ADDRESS SIGNALS
    2.
    发明申请
    TRAINING FOR MAPPING SWIZZLED DATA TO COMMAND/ADDRESS SIGNALS 有权
    培训将调度数据映射到命令/寻址信号

    公开(公告)号：US20140189224A1

    公开(公告)日：2014-07-03

    申请号：US13728581

    申请日：2012-12-27

    申请人： ALEXEY KOSTINSKY ,  ZVIKA GREENFIELD ,  CHRISTOPHER P. MOZAK ,  PAVEL KONEV ,  OLGA FOMENKO

    发明人： ALEXEY KOSTINSKY ,  ZVIKA GREENFIELD ,  CHRISTOPHER P. MOZAK ,  PAVEL KONEV ,  OLGA FOMENKO

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1072 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

    摘要： Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

    摘要翻译： 数据引脚映射和延迟训练技术。 在存储设备的命令/地址（CA）总线上检测到有效值。 响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。 信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位） 针脚。 分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。

    Memory Controller For Multi-Level System Memory With Coherency Unit
    3.
    发明申请
    Memory Controller For Multi-Level System Memory With Coherency Unit 审中-公开
    用于具有一致性单元的多级系统存储器的存储器控​​制器

    公开(公告)号：US20160283389A1

    公开(公告)日：2016-09-29

    申请号：US14671892

    申请日：2015-03-27

    申请人： ISRAEL DIAMAND ,  NIR MISGAV ,  ARAVINDH ANANTARAMAN ,  ZVIKA GREENFIELD

    发明人： ISRAEL DIAMAND ,  NIR MISGAV ,  ARAVINDH ANANTARAMAN ,  ZVIKA GREENFIELD

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811

    摘要： An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.

    摘要翻译： 描述了一种装置，其包括具有耦合到多级系统存储器的接口的存储器控​​制器。 存储器控制器还包括一致性缓冲器和一致性服务逻辑电路。 一致性缓冲区是为了保持已经接收到读取和/或写入请求的高速缓存行。 一致性服务逻辑电路耦合到接口和一致性缓冲器。 一致性服务逻辑电路是将已经被逐出的高速缓存行与多级系统存储器的级别的高速缓存行中的高速缓存行的另一版本合并在一起， 如果以下至少一个为真，则级别系统存储器：所述高速缓存行的另一版本处于修改状态; 存储器控制器具有针对高速缓存行的待决写入请求。

    SELECTIVE PREFETCHING FOR A SECTORED CACHE
    5.
    发明申请
    SELECTIVE PREFETCHING FOR A SECTORED CACHE 有权
    选择性推荐用于部署高速缓存

    公开(公告)号：US20150378919A1

    公开(公告)日：2015-12-31

    申请号：US14319533

    申请日：2014-06-30

    申请人： ARAVINDH V. ANANTARAMAN ,  ZVIKA GREENFIELD ,  ANANT V. NORI ,  JULIUS YULI MANDELBLAT

    发明人： ARAVINDH V. ANANTARAMAN ,  ZVIKA GREENFIELD ,  ANANT V. NORI ,  JULIUS YULI MANDELBLAT

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/602 ,  G06F2212/6028 ,  G06F2212/604

    摘要： A memory subsystem includes memory hierarchy that performs selective prefetching based on prefetch hints. A lower level memory detects a cache miss for a requested cache line that is part of a superline. The lower level memory generates a request vector for the cache line that triggered the cache miss, including a field for each cache line of the superline. The request vector includes a demand request for the cache line that caused the cache miss, and the lower level memory modifies the request vector with prefetch hint information. The prefetch hint information can indicate a prefetch request for one or more other cache lines in the superline. The lower level memory sends the request vector to the higher level memory with the prefetch hint information, and the higher level memory services the demand request and selectively either services a prefetch hint or drops the prefetch hint.

    摘要翻译： 存储器子系统包括基于预取提示来执行选择性预取的存储器层次。 较低级别的内存检测作为超级线路一部分的请求高速缓存行的高速缓存未命中。 较低级别的内存会为触发高速缓存未命中的高速缓存行生成一个请求向量，包括超级行的每个高速缓存行的一个字段。 请求向量包括引起高速缓存未命中的高速缓存行的请求请求，而下级存储器使用预取提示信息来修改请求向量。 预取提示信息可以指示超线中的一个或多个其它高速缓存行的预取请求。 较低级别的存储器使用预取提示信息将请求向量发送到较高级别的存储器，并且较高级别的存储器对请求请求进行服务，并且有选择地服务预取提示或丢弃预取提示。