摘要:
A jigging device that has a disk base and a pivot arm that has a sail attached. The pivot arm is attached to the pivot support. The pivot arm moves about a pivot assembly, moved by the wind. The sail is attached to the end of the pivot arm. At the other end, is a clip release. Fishing line, fed by a spool, passes through the disk and up to the clip release. The line is held there until sufficient downward force releases it from the clip. The line passes back down through the disk. A lure is attached to the end of the line. The lure is suspended in the water under the ice. The wind moves the pivot arm up and down, which causes the line and, consequently; the lure to move in sync with the pivot arm, thereby jigging the lure.
摘要:
Some embodiments disclose a remote support system having an analyzer and a communication link to connect to an event log associated with a monitored system. The analyzer is to monitor the event log over the link and to create a report using information in the event log. In response to the analyzer detecting a user-initiated service mode indication in the information the analyzer includes in the report additional information relating to the user-initiated service mode to facilitate events in the report to be ignored.
摘要:
A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.
摘要:
A method and apparatus is disclosed for determining the success of a proposed HIFU Treatment, of an ongoing HIFU Treatment, and/or of a completed HIFU Treatment. An energy density of a given HIFU Treatment may be used as a comparison factor between the given HIFU Treatment and other HIFU Treatments and as a predictor of the success of the given HIFU Treatment. One exemplary energy density is the amount of energy deposited in the treatment region divided by the volume of the treatment region. Another exemplary energy density is the amount of energy deposited in the treatment region divided by the pre-treatment mass of the treatment region. A method and apparatus is disclosed to detect the presence of focal hyperechoic features and non-focal hyperechoic features. A method and apparatus is disclosed to detect the presence of an acoustic obstruction.
摘要:
Method and system for allowing temporal navigation or time travel of data or data object across time are disclosed. In one embodiment, events that affected data objects are retrieved and inversed to revert the data objects back to a selected point-in-time, forward events are applied to move data objects to forward point-in-time. A sliding bar or a time dial allows a user to move data objects back and forward in time. Events that are applied may be a selected subset of events, altered events, new events, or events generated synthetically or any combinations thereof, for instance, to create counterfactual history.
摘要:
An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be coupled to overshoot-insensitive and undershoot-insensitive nodes of the logic circuitry, respectively. The undershoot-blocking module is operable to (i) receive from a first node of the logic circuitry a first signal event having a undershoot condition impressed thereon, and (ii) block it from passing to the overshoot-insensitive node. The overshoot-blocking module is operable to (i) receive from the first node a second signal event having an overshoot condition impressed thereon, and (ii) block it from passing to the undershoot-insensitive node. As such, further propagation of the overshoot and undershoot conditions are prevented.
摘要:
An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be coupled to overshoot-insensitive and undershoot-insensitive nodes of the logic circuitry, respectively. The undershoot-blocking module is operable to (i) receive from a first node of the logic circuitry a first signal event having a undershoot condition impressed thereon, and (ii) block it from passing to the overshoot-insensitive node. The overshoot-blocking module is operable to (i) receive from the first node a second signal event having an overshoot condition impressed thereon, and (ii) block it from passing to the undershoot-insensitive node. As such, further propagation of the overshoot and undershoot conditions are prevented.
摘要:
A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.