公开(公告)号：US5629703A

公开(公告)日：1997-05-13

申请号：US512797

申请日：1995-08-09

申请人： Roy W. Lewallen

发明人： Roy W. Lewallen

IPC分类号： H03M1/06 ,  H03M1/08 ,  H03M1/12

CPC分类号： H03M1/0614 ,  H03M1/12

摘要： A spectrum analyzer (10, 70) employs a method of reducing the amplitude of harmonic and spurious signals (102, 104, 112) introduced into a frequency-domain output spectrum by, for example, nonlinearities in a mixer (12, 78) or an ADC (20, 92). The method employs acquiring and digitizing a normal time-domain data record of an input signal, transforming the time-domain data record to a normal frequency-domain record (30), and storing the normal record. Next, a local oscillator (14, 76) driving the mixer is frequency shifted, and an additional time-domain data record is acquired, digitized, transformed, and stored to produce a shifted frequency-domain data record (40). Then, the shifted data record is mathematically realigned (50) with the normal data record and the normal and realigned data records are combined to produce a frequency-domain data record (60) having reduced harmonic and spurious signal amplitudes. The method preferably employs multiple frequency shifts of the local oscillator and a corresponding number of acquisitions, digitizations, transformations, realignments, and averages.

摘要翻译： 频谱分析仪（10,70）采用通过例如混频器（12,78）中的非线性来减小引入到频域输出频谱中的谐波和寄生信号（102,104,112）的振幅的方法或 ADC（20,92）。 该方法采用采集和数字化输入信号的正常时域数据记录，将时域数据记录变换为正常频域记录（30），并存储正常记录。 接下来，驱动混频器的本地振荡器（14,76）被频移，并且获取，数字化，变换和存储附加的时域数据记录以产生移位的频域数据记录（40）。 然后，移位的数据记录与正常数据记录在数学上重新对准（50），并且组合正常和重新排列的数据记录以产生具有减少的谐波和杂散信号幅度的频域数据记录（60）。 该方法优选地采用本地振荡器的多个频移以及相应数量的采集，数字化，变换，重新对齐和平均。

公开(公告)号：US5122734A

公开(公告)日：1992-06-16

申请号：US555212

申请日：1990-07-19

申请人： Roy W. Lewallen

发明人： Roy W. Lewallen

IPC分类号： G01R13/28 ,  G01R13/32 ,  H04R25/00

CPC分类号： G01R13/32

摘要： A method and apparatus prevents unwanted synchronization from obstructing a data acquisition instrument operator's view of N multiplexed signals synchronized to a high speed system clock being used to trigger an instrument through a prescaler with a fixed prescaling factor M, where N and M are related by a common factor. During a time while the instrument, for example, an oscilloscope, is ignoring trigger input information, a desynchronizing signal is applied to the prescaler, causing it to miss a random number of counts or causing it to count incorrectly. Thus, when the oscilloscope resumes triggering it is likely to be synchronized to a different combination of the multiplexed signals. This technique can be applied to individual data points or to records containing a number of data points. By accumulating a number of records obtained in this way and superimposing them on the display, or by simply displaying them very rapidly so that the averaging effects of the human eye cause them to appear to be superimposed, these composite records effectively include complete information about the full set of multiplexed signals.

摘要翻译： 一种方法和装置防止不期望的同步妨碍数据采集仪器操作者对与用于通过具有固定预分频因子M的预分频器触发仪器的高速系统时钟同步的N个多路复用信号的视图，其中N和M通过 公约数。 在仪器（例如示波器）的某段时间内，忽略触发输入信息，将一个去同步信号施加到预分频器，导致它错过随机数的计数或导致计数不正确。 因此，当示波器恢复触发时，它可能被同步到多路复用信号的不同组合。 该技术可以应用于单个数据点或包含多个数据点的记录。 通过累积以这种方式获得的许多记录并将其叠加在显示器上，或者通过简单地显示它们，使得人眼的平均效果使它们看起来被叠加，这些复合记录有效地包括关于 全套复用信号。

公开(公告)号：US3950607A

公开(公告)日：1976-04-13

申请号：US355802

申请日：1973-04-30

申请人： Glen R. Southworth ,  Roy W. Lewallen ,  John E. Sparks

发明人： Glen R. Southworth ,  Roy W. Lewallen ,  John E. Sparks

IPC分类号： H04N7/26 ,  H04B1/66 ,  H04N7/088 ,  H04N7/12

CPC分类号： H04B1/66 ,  H04N7/088 ,  H04N7/125

摘要： A method and apparatus is disclosed for converting a wide-bandwidth signal to a narrow-bandwidth signal, the disclosed method and apparatus being particularly well suited for converting a wide-bandwidth real-time television signal to a narrow-bandwidth signal. A sampled video signal is coupled to an analog-to-digital converter which converts the amplitude of each sampled element to a binary code word having a predetermined number of bits. The binary code words are then written into a buffer storage element controlled by a clock switching device and later clocked out of the buffer storage device at a clock rate less than the input rate with the output from the buffer storage device being coupled to a digital-to-analog converter whose output is an analog signal with the same amplitude variations as the sampled video signal but with a time base stretched out by a predetermined factor. The field, either odd or even interlace, from which the sampled video signal was taken is identified by ascertaining the location of the horizontal signal pulses relative to the vertical signal pulse, and this field index may then be used to code the output narrow-bandwidth video signal. Another embodiment is disclosed which utilizes an analog shift register as the buffer storage device in place of the digital buffer storage with its attached analog-to-digital and digital-to-analog converter. An alternate embodiment is disclosed which utilizes a pair of parallel connected buffer storage units (either digital or analog) controlled by output gating to provide for a continuous non-interlaced narrow-bandwidth signal.

摘要翻译： 公开了一种用于将宽带宽信号转换为窄带宽信号的方法和装置，所公开的方法和装置特别适用于将宽带宽实时电视信号转换为窄带宽信号。 采样视频信号耦合到模数转换器，其将每个采样元件的振幅转换为具有预定位数的二进制码字。 然后将二进制码字写入由时钟切换装置控制的缓冲存储元件中，并随后以比输入速率低的时钟速率从缓冲存储装置输出，其中缓冲存储装置的输出耦合到数字 - 模拟转换器，其输出是具有与采样视频信号相同幅度变化的模拟信号，但时间延长了预定因子。 通过确定水平信号脉冲相对于垂直信号脉冲的位置来识别取样视频信号的奇数或偶数交错场，然后该场指数可用于对输出窄带宽进行编码 视频信号。 公开了另一个实施例，其利用模拟移位寄存器作为缓冲存储装置，代替其附接的模拟数字和数模转换器的数字缓冲存储器。 公开了一种替代实施例，其利用由输出门控控制的一对并联连接的缓冲存储单元（数字或模拟）来提供连续的非隔行窄带宽信号。

公开(公告)号：US4924110A

公开(公告)日：1990-05-08

申请号：US241686

申请日：1988-09-08

申请人： John B. Rettig ,  Jonathan Lueker ,  John E. Carlson ,  Stanley P. Kaveckis ,  Roy W. Lewallen

发明人： John B. Rettig ,  Jonathan Lueker ,  John E. Carlson ,  Stanley P. Kaveckis ,  Roy W. Lewallen

IPC分类号： H03K3/02 ,  H03K17/04 ,  H03K17/74

CPC分类号： H03K17/04 ,  H03K17/74

摘要： A step generator for producing steps having constant edge parameters while driving varying loads includes a pair of DC coupled low speed diode switches for slowly switching the output load current. A pair of capacitors provide an AC coupled high speed input for rapidly, but temporarily, switching the output load current until the sustaining action of the low speed diode switch has occurred. A pair of resistor divider circuits in each of the low speed diode switches maintains a relatively constant reverse bias voltage across the diodes coupled to the capacitors. The high speed switching threshold is maintained at a relatively constant level which produces an output voltage step with constant edge parameters and no overshoot.