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公开(公告)号：US08754713B2
公开(公告)日：2014-06-17
申请号：US12952705
申请日：2010-11-23
申请人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/00
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译： 在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。 反馈回路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制 基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。 在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。
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公开(公告)号：US07859344B2
公开(公告)日：2010-12-28
申请号：US12111458
申请日：2008-04-29
申请人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/00
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译： 在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。 反馈环路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制 基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。 在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。
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公开(公告)号：US20090267664A1
公开(公告)日：2009-10-29
申请号：US12111458
申请日：2008-04-29
申请人： Toshiya UOZUMI , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P. Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya UOZUMI , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P. Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/06
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译： 在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。 反馈环路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制 基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。 在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。
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公开(公告)号：US20100097150A1
公开(公告)日：2010-04-22
申请号：US12252443
申请日：2008-10-16
申请人： Keisuke Ueda , Toshiya Uozumi , Satoru Yamamoto , Mitsunori Samata , Russell P. Mohn , Aleksander Dec , Ken Suyama
发明人： Keisuke Ueda , Toshiya Uozumi , Satoru Yamamoto , Mitsunori Samata , Russell P. Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/08
CPC分类号： H03L7/1976 , H03L7/089 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal.
摘要翻译： 提供一种用于抑制由于在PLL电路中对模拟电路进行数字化而产生的量化噪声的技术。 PLL电路包括：数字相位频率检测器，其检测（比较）参考信号的相位和频率以及分频信号，并将其转换为数字值; 数字环路滤波器，其从数字相位频率比较器的输出消除高频噪声分量; 数字模拟转换器，其将数字环路滤波器的输出的数字值转换为模拟值; 模拟滤波器，其从数字 - 模拟转换器的输出消除高频噪声分量; 基于模拟滤波器的输出来控制频率的压控振荡器; 以及分频器，其分压电压控制振荡器的频率并输出分频信号。
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公开(公告)号：US20130300477A1
公开(公告)日：2013-11-14
申请号：US13982249
申请日：2011-01-26
申请人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
发明人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
IPC分类号： H03L7/093
CPC分类号： H04L7/0332 , H03L7/07 , H03L7/093 , H03L7/099 , H03L7/0991 , H03L7/10 , H03L7/103 , H03L7/105 , H03L7/1075 , H03L7/18 , H03L2207/06 , H03L2207/50 , H04L7/0337
摘要： A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.
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公开(公告)号：US09154143B2
公开(公告)日：2015-10-06
申请号：US13982249
申请日：2011-01-26
申请人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
发明人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
CPC分类号： H04L7/0332 , H03L7/07 , H03L7/093 , H03L7/099 , H03L7/0991 , H03L7/10 , H03L7/103 , H03L7/105 , H03L7/1075 , H03L7/18 , H03L2207/06 , H03L2207/50 , H04L7/0337
摘要： A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.
摘要翻译： 半导体器件包括受控振荡器和控制单元。 受控振荡器包括谐振电路，放大单元和电流调节单元。 谐振电路包括一个或多个电感器和具有可变电容值的第一电容单元。 放大单元连接到谐振电路，并且输出具有与谐振电路的谐振频率相对应的振荡频率的本地振荡信号。 电流调节单元调节要提供给放大单元的驱动电流的值。 控制单元控制第一电容单元和电流调节单元的电容值。 当控制单元指示当前调整单元改变要提供给放大单元的驱动电流的值时，控制单元也改变第一电容单元的电容值。
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7.发明授权公开(公告)号：US08929502B2
公开(公告)日：2015-01-06
申请号：US13560639
申请日：2012-07-27
申请人： Ryo Endo , Keisuke Ueda , Toshiya Uozumi
发明人： Ryo Endo , Keisuke Ueda , Toshiya Uozumi
CPC分类号： H04L7/033 , H03K23/662 , H03L7/0992 , H04L27/0014 , H04L2027/0016 , H04L2027/0022 , H04L2027/0036 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0087
摘要： To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.
摘要翻译： 为了减少高频信号处理装置和各自配置有数字型PLL电路的无线通信系统中的杂散的影响。 在包括数字相位比较器单元，数字低通滤波器，数字控制振荡器单元和多模块驱动器单元（分频器单元）的数字型PLL电路中，数字相位中的时钟信号的时钟频率 比较器单元可选地配置在多个选项中。 根据为数字控制振荡器单元的振荡输出信号设定标准的哪个频带，选择作为参考频率的整数倍的频率的时钟频率。
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公开(公告)号：US20130051290A1
公开(公告)日：2013-02-28
申请号：US13560639
申请日：2012-07-27
申请人： Ryo ENDO , Keisuke Ueda , Toshiya Uozumi
发明人： Ryo ENDO , Keisuke Ueda , Toshiya Uozumi
CPC分类号： H04L7/033 , H03K23/662 , H03L7/0992 , H04L27/0014 , H04L2027/0016 , H04L2027/0022 , H04L2027/0036 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0087
摘要： To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.
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公开(公告)号：US08331520B2
公开(公告)日：2012-12-11
申请号：US12790319
申请日：2010-05-28
申请人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
发明人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/0802 , H03L7/1077 , H03L7/18 , H03L2207/50
摘要： A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.
摘要翻译： 提供同时满足低功耗和小型化的PLL电路。 PLL电路的相位比较器包括计数器和时间 - 数字转换器。 计数器接收通过对数字控制振荡器的输出和高频时钟信号进行分频而获得的参考时钟信号和低频时钟信号。 该计数器通过对高频时钟信号的时钟数进行计数来检测参考时钟信号和低频时钟信号之间的相位差。 时间 - 数字转换器接收参考时钟信号和低频时钟信号。 时间数字转换器在计数器的输出达到预定范围之后，将参考时钟信号和低频时钟信号之间的相位差检测到比高频时钟信号的周期短的时间段的精度。
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公开(公告)号：US20110007859A1
公开(公告)日：2011-01-13
申请号：US12790319
申请日：2010-05-28
申请人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
发明人： Keisuke Ueda , Toshiya Uozumi , Ryo Endo
CPC分类号： H03L7/085 , H03L7/0802 , H03L7/1077 , H03L7/18 , H03L2207/50
摘要： A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.
摘要翻译： 提供同时满足低功耗和小型化的PLL电路。 PLL电路的相位比较器包括计数器和时间 - 数字转换器。 计数器接收通过对数字控制振荡器的输出和高频时钟信号进行分频而获得的参考时钟信号和低频时钟信号。 该计数器通过对高频时钟信号的时钟数进行计数来检测参考时钟信号和低频时钟信号之间的相位差。 时间 - 数字转换器接收参考时钟信号和低频时钟信号。 时间数字转换器在计数器的输出达到预定范围之后，将参考时钟信号和低频时钟信号之间的相位差检测到比高频时钟信号的周期短的时间段的精度。
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