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    Methods of forming integrated circuit devices using modified rectangular mask patterns to increase reliability of contacts to electrically conductive lines
    1.
    发明授权
    Methods of forming integrated circuit devices using modified rectangular mask patterns to increase reliability of contacts to electrically conductive lines 有权
    使用改进的矩形掩模图案形成集成电路器件以提高与导电线的接触的可靠性的方法

    公开(公告)号：US08796134B2

    公开(公告)日：2014-08-05

    申请号：US13397038

    申请日：2012-02-15

    申请人： Chang-Hwa Kim ,  Ryan L. Burns

    发明人： Chang-Hwa Kim ,  Ryan L. Burns

    IPC分类号： H01L21/4763 ,  H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0274

    摘要： Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects.

    摘要翻译： 形成集成电路器件的方法包括在集成电路衬底上的并排位置形成第一和第二导电线。 执行步骤以选择性地将第一和第二导电线中的每一个蚀刻成具有彼此分离的具有相对端的相应的一对互连。 该选择性蚀刻步骤使用其上具有改变的矩形掩模图案的光刻掩模进行，其被配置为限定该对互连中的每一个的相对端的形状。

    Substrate planarization with imprint materials and processes
    3.
    发明授权
    Substrate planarization with imprint materials and processes 有权
    基板平面化与压印材料和工艺

    公开(公告)号：US08084185B2

    公开(公告)日：2011-12-27

    申请号：US12350250

    申请日：2009-01-08

    申请人： Sean D. Burns ,  Colin J. Brodsky ,  Ryan L. Burns

    发明人： Sean D. Burns ,  Colin J. Brodsky ,  Ryan L. Burns

    IPC分类号： G03F7/00 ,  G03F7/004 ,  G03F7/26 ,  G03F7/40

    CPC分类号： G03F7/027 ,  G03F7/094 ,  G03F7/168

    摘要： The present invention relates to planarization materials and methods of using the same for substrate planarization in photolithography. A planarization layer of a planarization composition is formed on a substrate. The planarization composition contains at least one aromatic monomer and at least one non-aromatic monomer. A substantially flat surface is brought into contact with the planarization layer. The planarization layer is cured by exposing to a first radiation or by baking. The substantially flat surface is then removed. A photoresist layer is formed on the planarization layer. The photoresist layer is exposed to a second radiation followed by development to form a relief image in the photoresist layer. The relief image is then transferred into the substrate.

    摘要翻译： 本发明涉及平面化材料及其在光刻中用于衬底平面化的方法。 在基板上形成平坦化组合物的平坦化层。 平坦化组合物含有至少一种芳族单体和至少一种非芳族单体。 基本平坦的表面与平坦化层接触。 平坦化层通过暴露于第一辐射或通过烘烤而固化。 然后去除基本平坦的表面。 在平坦化层上形成光致抗蚀剂层。 将光致抗蚀剂层暴露于第二辐射，随后显影以在光致抗蚀剂层中形成浮雕图像。 然后将浮雕图像转移到基底中。

    PERFORMING OPTICAL PROXIMITY CORRECTION BY INCORPORATING CRITICAL DIMENSION CORRECTION
    4.
    发明申请
    PERFORMING OPTICAL PROXIMITY CORRECTION BY INCORPORATING CRITICAL DIMENSION CORRECTION 有权
    通过引入关键尺寸校正来执行光学近似校正

    公开(公告)号：US20100199256A1

    公开(公告)日：2010-08-05

    申请号：US12697556

    申请日：2010-02-01

    申请人： Ryan L. Burns ,  Sean D. Burns

    发明人： Ryan L. Burns ,  Sean D. Burns

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/70466 ,  G03F7/705 ,  G06F2217/12

    摘要： A solution for performing an optical proximity correction (OPC) process on a layout by incorporating a critical dimension (CD) correction is provided. A method may include separating the layout into a first portion and a second portion corresponding to the two exposures; creating a model for calculating a CD correction for a site on the first portion, the model corresponding to a topography change on the site due to the double exposures; implementing an OPC iteration for the fragment based on the model to generate an OPC solution for the first portion; and combining the OPC solution for the first portion with an OPC solution for the second portion to generate an OPC solution for the layout to generate a mask for fabricating a structure using the layout.

    摘要翻译： 提供了通过结合临界尺寸（CD）校正在布局上执行光学邻近校正（OPC）处理的解决方案。 方法可以包括将布局分离成对应于两次曝光的第一部分和第二部分; 创建用于计算第一部分上的站点的CD校正的模型，该模型对应于由于双重曝光而在现场的地形变化; 基于模型实现片段的OPC迭代，以生成第一部分的OPC解决方案; 并将第一部分的OPC解决方案与用于第二部分的OPC解决方案组合，以生成用于布局的OPC解决方案，以生成用于使用布局制造结构的掩模。

    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES USING MODIFIED RECTANGULAR MASK PATTERNS TO INCREASE RELIABILITY OF CONTACTS TO ELECTRICALLY CONDUCTIVE LINES
    5.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES USING MODIFIED RECTANGULAR MASK PATTERNS TO INCREASE RELIABILITY OF CONTACTS TO ELECTRICALLY CONDUCTIVE LINES 有权
    使用改进的矩形掩模图形成集成电路设备的方法来提高联系人对导电线路的可靠性

    公开(公告)号：US20130210223A1

    公开(公告)日：2013-08-15

    申请号：US13397038

    申请日：2012-02-15

    申请人： Chang-Hwa Kim ,  Ryan L. Burns

    发明人： Chang-Hwa Kim ,  Ryan L. Burns

    IPC分类号： H01L21/768

    CPC分类号： H01L21/32139 ,  H01L21/0274

    摘要： Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects.

    摘要翻译： 形成集成电路器件的方法包括在集成电路衬底上的并排位置形成第一和第二导电线。 执行步骤以选择性地将第一和第二导电线中的每一个蚀刻成具有彼此分离的具有相对端的相应的一对互连。 该选择性蚀刻步骤使用其上具有改变的矩形掩模图案的光刻掩模进行，其被配置为限定该对互连中的每一个的相对端的形状。

    SUBSTRATE PLANARIZATION WITH IMPRINT MATERIALS AND PROCESSES
    6.
    发明申请
    SUBSTRATE PLANARIZATION WITH IMPRINT MATERIALS AND PROCESSES 有权
    基材平面化与印刷材料和工艺

    公开(公告)号：US20100173247A1

    公开(公告)日：2010-07-08

    申请号：US12350250

    申请日：2009-01-08

    申请人： Sean D. Burns ,  Colin J. Brodsky ,  Ryan L. Burns

    发明人： Sean D. Burns ,  Colin J. Brodsky ,  Ryan L. Burns

    IPC分类号： G03F7/027 ,  G03F7/20 ,  G03F7/36

    CPC分类号： G03F7/027 ,  G03F7/094 ,  G03F7/168

    摘要： The present invention relates to planarization materials and methods of using the same for substrate planarization in photolithography. A planarization layer of a planarization composition is formed on a substrate. The planarization composition contains at least one aromatic monomer and at least one non-aromatic monomer. A substantially flat surface is brought into contact with the planarization layer. The planarization layer is cured by exposing to a first radiation or by baking The substantially flat surface is then removed. A photoresist layer is formed on the planarization layer. The photoresist layer is exposed to a second radiation followed by development to form a relief image in the photoresist layer. The relief image is then transferred into the substrate.

    摘要翻译： 本发明涉及平面化材料及其在光刻中用于衬底平面化的方法。 在基板上形成平坦化组合物的平坦化层。 平坦化组合物含有至少一种芳族单体和至少一种非芳族单体。 基本平坦的表面与平坦化层接触。 平坦化层通过暴露于第一辐射或通过烘烤而固化。然后去除基本平坦的表面。 在平坦化层上形成光致抗蚀剂层。 将光致抗蚀剂层暴露于第二辐射，随后显影以在光致抗蚀剂层中形成浮雕图像。 然后将浮雕图像转移到基底中。

    Performing optical proximity correction by incorporating critical dimension correction
    7.
    发明授权
    Performing optical proximity correction by incorporating critical dimension correction 有权
    通过引入关键尺寸校正来执行光学邻近校正

    公开(公告)号：US08302034B2

    公开(公告)日：2012-10-30

    申请号：US12697556

    申请日：2010-02-01

    申请人： Ryan L. Burns ,  Sean D. Burns

    发明人： Ryan L. Burns ,  Sean D. Burns

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/70466 ,  G03F7/705 ,  G06F2217/12

    摘要： A solution for performing an optical proximity correction (OPC) process on a layout by incorporating a critical dimension (CD) correction is provided. A method may include separating the layout into a first portion and a second portion corresponding to the two exposures; creating a model for calculating a CD correction for a site on the first portion, the model corresponding to a topography change on the site due to the double exposures; implementing an OPC iteration for the fragment based on the model to generate an OPC solution for the first portion; and combining the OPC solution for the first portion with an OPC solution for the second portion to generate an OPC solution for the layout to generate a mask for fabricating a structure using the layout.

    摘要翻译： 提供了通过结合临界尺寸（CD）校正在布局上执行光学邻近校正（OPC）处理的解决方案。 方法可以包括将布局分离成对应于两次曝光的第一部分和第二部分; 创建用于计算第一部分上的站点的CD校正的模型，该模型对应于由于双重曝光而在现场的地形变化; 基于模型实现片段的OPC迭代，以生成第一部分的OPC解决方案; 并将第一部分的OPC解决方案与用于第二部分的OPC解决方案组合，以生成用于布局的OPC解决方案，以生成用于使用布局制造结构的掩模。

    Dithiolene functionalized polymer membrane for olefin/paraffin separation
    8.
    发明授权
    Dithiolene functionalized polymer membrane for olefin/paraffin separation 失效
    用于烯烃/石蜡分离的二硫戊烯官能化聚合物膜

    公开(公告)号：US07160356B2

    公开(公告)日：2007-01-09

    申请号：US10824772

    申请日：2004-04-15

    申请人： William J. Koros ,  Ryan L. Burns

    发明人： William J. Koros ,  Ryan L. Burns

    IPC分类号： B01D53/22 ,  B01D61/00 ,  B01D69/00 ,  B01D71/56

    CPC分类号： B01D67/0011 ,  B01D53/228 ,  B01D69/12 ,  B01D69/142 ,  B01D71/56 ,  B01D71/62 ,  B01D71/64 ,  B01D2257/7022 ,  B01D2325/022 ,  C07C7/144 ,  C07C11/02

    摘要： A polymeric composite may be used for forming fluid separation membranes. The membranes may be formed from polyimide, polyamide or poly (pyrrolone-imide) materials. Polyamides may be formed by the condensation of a tetraamine, a tetraacid, and a diamine. Polyimides and poly (pyrrolone-imides) may be formed by the cyclization of a polymer precursor. A polymeric composite may include a dithiolene or a mixture of dithiolenes. A polymer matrix incorporating dithiolenes may exhibit an olefin/paraffin solubility selectivity. A solubility selectivity may be between about 1.1 and about 2.0.

    摘要翻译： 聚合物复合材料可用于形成流体分离膜。 膜可以由聚酰亚胺，聚酰胺或聚（吡咯酮 - 酰亚胺）材料形成。 聚酰胺可以通过四胺，四酸和二胺的缩合形成。 聚酰亚胺和聚（吡咯烷酮 - 酰亚胺）可以通过聚合物前体的环化形成。 聚合物复合材料可以包括二硫戊烯或二硫戊烯的混合物。 掺入二硫戊烯的聚合物基质可以表现出烯烃/链烷烃的溶解度选择性。 溶解度选择性可以在约1.1和约2.0之间。