公开(公告)号：US20130147558A1

公开(公告)日：2013-06-13

申请号：US13446397

申请日：2012-04-13

Applicant: Sang-Yeon BYEON

Inventor： Sang-Yeon BYEON

IPC: H03F3/45

CPC classification number: H03K19/00361 ,  G11C7/1084 ,  H03F3/3022 ,  H03F2203/30042 ,  H03F2203/30051 ,  H03F2203/30057

Abstract: A buffer circuit includes an amplification unit configured to amplify and output a difference between an input signal and a reference voltage; and a driver configured to drive an output node in response to the output of the amplification unit and be controlled in at least one of a pull-up driving strength and a pull-down driving strength at the output node in response to the reference voltage.

Abstract translation: 缓冲电路包括：放大单元，被配置为放大和输出输入信号和参考电压之间的差; 以及驱动器，被配置为响应于放大单元的输出来驱动输出节点，并且响应于参考电压而在输出节点处被控制为上拉驱动强度和下拉驱动强度中的至少一个。

公开(公告)号：US20120105156A1

公开(公告)日：2012-05-03

申请号：US13217391

申请日：2011-08-25

Applicant: Sang Yeon BYEON

Inventor： Sang Yeon BYEON

IPC: H03F3/45

CPC classification number: H03K3/00 ,  H03K3/0375 ,  H03K19/0175

Abstract: A receiver circuit of a semiconductor apparatus includes a first sense amplifier, a level restriction unit, and a second sense amplifier. The first sense amplifier amplifies an input signal in response to a clock signal and generates a first signal with a voltage swing between a first level and a second level. The level restriction unit receives the first signal and generates a correction signal with a voltage swing between the first level and a third level. The second sense amplifier amplifies the correction signal in response to the clock signal and generates a second signal with the voltage swing between the first level and the second level.

Abstract translation: 半导体装置的接收器电路包括第一读出放大器，电平限制单元和第二读出放大器。 第一读出放大器响应于时钟信号放大输入信号，并产生具有第一电平和第二电平之间的电压摆幅的第一信号。 电平限制单元接收第一信号并产生具有在第一电平和第三电平之间的电压摆幅的校正信号。 第二读出放大器响应于时钟信号放大校正信号，并产生具有第一电平和第二电平之间的电压摆幅的第二信号。

公开(公告)号：US20110211416A1

公开(公告)日：2011-09-01

申请号：US13105414

申请日：2011-05-11

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C8/18

CPC classification number: H03H11/26

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

公开(公告)号：US07965582B2

公开(公告)日：2011-06-21

申请号：US12157287

申请日：2008-06-09

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C8/18

CPC classification number: H03H11/26

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract translation: 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

公开(公告)号：US20090116601A1

公开(公告)日：2009-05-07

申请号：US12005850

申请日：2007-12-28

Applicant: Kyung-Hoon Kim ,  Jong-Ho Kang ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Sang-Yeon Byeon

Inventor： Kyung-Hoon Kim ,  Jong-Ho Kang ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Sang-Yeon Byeon

IPC: H04L7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093

Abstract: A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Abstract translation: 时钟数据恢复（CDR）电路占据了高集成度半导体器件，电子器件和系统所需的较小面积，并且易于进行设计修改。 CDR电路包括：数字滤波器，被配置为滤波在预定周期期间接收到的相位比较结果信号和输出控制信号;驱动器，被配置为通过调整预定周期来控制数字滤波器;以及输入/输出电路，被配置为识别输入和输出 的数据和时钟响应于控制信号。

公开(公告)号：US20080238512A1

公开(公告)日：2008-10-02

申请号：US12001923

申请日：2007-12-12

Applicant: Sang-Yeon Byeon

Inventor： Sang-Yeon Byeon

IPC: H03K3/00 ,  H03L7/00

CPC classification number: H03L7/06 ,  H03K5/135 ,  H03M9/00 ,  H04J3/047 ,  H04J3/0685

Abstract: A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.

Abstract translation: 用于数据对准的电路包括第一锁存单元和第二锁存单元。 第一锁存单元通过使用具有不同相位和相同频率的多个第一时钟来锁存串行输入数据以输出锁存数据。 第二锁存单元通过使用频率低于第一时钟和更多个不同相位的多个第二时钟来锁存来自第一锁存单元的数据，从而输出并行数据。

公开(公告)号：US20110156754A1

公开(公告)日：2011-06-30

申请号：US12704871

申请日：2010-02-12

Applicant: Sang-Yeon BYEON

Inventor： Sang-Yeon BYEON

IPC: H03K19/096 ,  H03K19/094

CPC classification number: H03K19/096 ,  H03M9/00

Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Abstract translation: 半导体器件包括多个CML缓冲单元，其被配置为以对应于多相源时钟的顺序并行地缓冲多个串行应用的数据信号到CML级; 以及CMOS放大块，被配置为响应于多相源时钟将从多个CML缓冲单元顺序地输出的多个缓冲数据信号放大到CMOS电平，并且在相同的定时并行输出放大的数据信号。

公开(公告)号：US08476933B2

公开(公告)日：2013-07-02

申请号：US13217391

申请日：2011-08-25

Applicant: Sang Yeon Byeon

Inventor： Sang Yeon Byeon

IPC: G01R19/00 ,  G11C11/34

CPC classification number: H03K3/00 ,  H03K3/0375 ,  H03K19/0175

Abstract: A receiver circuit of a semiconductor apparatus includes a first sense amplifier, a level restriction unit, and a second sense amplifier. The first sense amplifier amplifies an input signal in response to a clock signal and generates a first signal with a voltage swing between a first level and a second level. The level restriction unit receives the first signal and generates a correction signal with a voltage swing between the first level and a third level. The second sense amplifier amplifies the correction signal in response to the clock signal and generates a second signal with the voltage swing between the first level and the second level.

Abstract translation: 半导体装置的接收器电路包括第一读出放大器，电平限制单元和第二读出放大器。 第一读出放大器响应于时钟信号放大输入信号，并产生具有第一电平和第二电平之间的电压摆幅的第一信号。 电平限制单元接收第一信号并产生具有在第一电平和第三电平之间的电压摆幅的校正信号。 第二读出放大器响应于时钟信号放大校正信号，并产生具有第一电平和第二电平之间的电压摆幅的第二信号。

公开(公告)号：US08238193B2

公开(公告)日：2012-08-07

申请号：US13105414

申请日：2011-05-11

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C8/18

CPC classification number: H03H11/26

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract translation: 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

公开(公告)号：US07710794B2

公开(公告)日：2010-05-04

申请号：US12215738

申请日：2008-06-30

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076

Abstract: A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.

Abstract translation: 考虑到实际时钟/数据路径的延迟时间，半导体存储器件可以具有期望的内部时钟。 半导体存储器件包括多锁信号产生单元，被配置为接收参考时钟信号并产生彼此具有恒定相位差的多个时钟信号;延迟建模单元，被配置为通过反映延迟来产生多个延迟时钟信号 选择信号生成单元，被配置为通过比较参考时钟信号和多个延迟时钟信号之间的相位来产生选择信号;以及相位多路复用单元，被配置为输出任意的时钟/数据路径， 所述多个时钟信号中的一个作为响应于所述选择信号的最终时钟信号。