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公开(公告)号:US20240146402A1
公开(公告)日:2024-05-02
申请号:US18201821
申请日:2023-05-25
发明人: Paul RUTT , Erik Buehler , Damon Van Buren
CPC分类号: H04B7/18515 , H04B1/0007 , H04B1/0014 , H04B1/0039 , H04B1/0042 , H04B1/0046 , H04B1/40 , H04B1/44 , H04B7/08 , H04B7/1851 , H04B7/212
摘要: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
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公开(公告)号:US20200220613A1
公开(公告)日:2020-07-09
申请号:US16286567
申请日:2019-02-26
发明人: PAUL RUTT , JESSE D. HOBART , RICHARD E. PEREGO
摘要: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.
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公开(公告)号:US10461753B1
公开(公告)日:2019-10-29
申请号:US15978017
申请日:2018-05-11
IPC分类号: H03L7/00
摘要: Systems and methods for synchronizing the clocks of a central device and one or more destination devices are disclosed. In some embodiments the central device and destination devices are implemented in a space-based or high-altitude asset. The central device provides a series of synchronization pulses to the one or more destination devices. In response to detecting, at the destination device, the synchronization pulse, a sample of the destination device clock is stored in a register. The sample is provided to the central device. The sequence is repeated at least once. A phase offset between the central device clock and the destination device clock may be determined based on the returned samples and the position of the samples within the register.
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公开(公告)号:US20180241503A1
公开(公告)日:2018-08-23
申请号:US15897927
申请日:2018-02-15
发明人: W. Reagan Harper
摘要: Systems and methods for implementing robust, reliable distributed data storage across satellites and or among terrestrial and space-based assets are described. In some examples, data is erasure encoded prior to storage to improve reliability while minimizing storage capacity requirements. In some examples, erasure encoded data is stored across a combination of satellites and terrestrial assets in a manner that prohibits reconstruction of the data using only encoded data on the ground. In some examples, an erasure encoding fragment size is selected based on a write page size of a solid state device to extend device life.
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公开(公告)号:US20170264360A1
公开(公告)日:2017-09-14
申请号:US15456086
申请日:2017-03-10
发明人: ERIK BUEHLER
摘要: A satellite communication system processes a plurality of input signals to generate beamformed signals, drives a plurality of nonlinear power amplifiers with the beamformed input signals to produce RF signals for transmission; and transmits the RF signals with a plurality of Tx antenna elements. Conversion to and from linear signals to and from nonlinear or digitized signals is performed. Temporal or spatial decorrelation of the beamformed signals is employed to reduce the impact of intermodulation products. In some cases the power amplifiers are nonlinear, and can be one-sided or two-sided and produce two or three distinct output levels.
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公开(公告)号:US20220271830A1
公开(公告)日:2022-08-25
申请号:US17668177
申请日:2022-02-09
发明人: Paul RUTT , Erik Buehler , Damon Van Buren
摘要: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
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公开(公告)号:US11329718B2
公开(公告)日:2022-05-10
申请号:US17142778
申请日:2021-01-06
发明人: Paul Rutt , Erik Buehler , Damon Van Buren
摘要: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.
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公开(公告)号:US10917163B2
公开(公告)日:2021-02-09
申请号:US16286567
申请日:2019-02-26
发明人: Paul Rutt , Jesse D. Hobart , Richard E. Perego
摘要: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.
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公开(公告)号:US10243650B2
公开(公告)日:2019-03-26
申请号:US15263134
申请日:2016-09-12
发明人: Erik Buehler , Damon Van Buren , Paul Rutt
摘要: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
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公开(公告)号:US09690646B2
公开(公告)日:2017-06-27
申请号:US14812871
申请日:2015-07-29
发明人: Erik Buehler
CPC分类号: G06F11/079 , G06F11/0706 , G06F11/0751 , H03M9/00 , H03M13/03 , H03M13/096 , H03M13/098 , H04L1/0022 , H04L1/0045 , H04L1/0061 , H04L1/16 , H04L1/22 , H04L2001/0096
摘要: Light-weight, configurable error detection in a satellite communication system that detects invalid SerDes lanes via hash codes appended to packets of data in the lanes. An indication can be passed back upstream about the invalid lane so that the lane can be reset. Error correction can be provided by reconstructing the bit data in the invalid SerDes lane based on parity information in an optional parity lane.
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