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公开(公告)号：US20220108975A1
公开(公告)日：2022-04-07
申请号：US17492356
申请日：2021-10-01
Applicant: STMICROELECTRONICS S.r.l. , STMICROELECTRONICS S.r.l.
Inventor： Cristina MANOLA , Rosa Lucia TORRISI , Simone RASCUNÀ , Gabriele BELLOCCHI , Annalinda CONTINO , Giuseppe MACCARRONE
IPC: H01L23/00 , H01L23/495 , B22F9/24 , B22F1/00
Abstract: The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200° C. and in some embodiments at about 150° C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.
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公开(公告)号：US12260910B2
公开(公告)日：2025-03-25
申请号：US18148380
申请日：2022-12-29
Applicant: STMICROELECTRONICS S.r.l.
IPC: G11C13/00
Abstract: The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.
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公开(公告)号：US12218231B2
公开(公告)日：2025-02-04
申请号：US17116465
申请日：2020-12-09
Applicant: STMicroelectronics S.r.l.
Inventor： Ferdinando Iucolano , Alessandro Chini
IPC: H01L29/778 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/66
Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.
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公开(公告)号：US12216488B2
公开(公告)日：2025-02-04
申请号：US17507545
申请日：2021-10-21
Applicant: STMicroelectronics S.r.l.
Inventor： Domenico Tripodi
Abstract: A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal.
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5.发明申请公开(公告)号：US20250038060A1
公开(公告)日：2025-01-30
申请号：US18917464
申请日：2024-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Simone RASCUNA' , Claudio CHIBBARO , Alfio GUARNERA , Mario Giuseppe SAGGIO , Francesco LIZIO
Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
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Patent Agency Ranking
公开(公告)号：US12211772B2
公开(公告)日：2025-01-28
申请号：US17688013
申请日：2022-03-07
Applicant: STMicroelectronics S.r.l. , STMicroelectronics, Inc.
IPC: H01L23/495 , H01L21/56 , H01L23/16 , H01L23/31 , H01L23/00
Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.
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公开(公告)号：US12210089B2
公开(公告)日：2025-01-28
申请号：US18418298
申请日：2024-01-21
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Andrea Cavarra , Alessandro Finocchiaro , Giuseppe Papotto , Giuseppe Palmisano
Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·Δf, where M is an integer from 0 to N−1, where N is a number of intervals into which a frequency range for the output signal is divided, and where Δf is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.
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公开(公告)号：US20250028342A1
公开(公告)日：2025-01-23
申请号：US18907071
申请日：2024-10-04
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto Cattani , Alessandro Gasparini , Stefano Ramorini
IPC: G05F1/56
Abstract: In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.
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公开(公告)号：US12206778B2
公开(公告)日：2025-01-21
申请号：US17857633
申请日：2022-07-05
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Ruggero Susella
IPC: H04L9/08
Abstract: One or more keys are derived from a master key by executing a plurality of encryption operations. A first encryption operation uses the master key to encrypt a plaintext input having a plurality of bytes. Multiple intermediate encryption operations are performed using a respective intermediate key generated by a previous encryption operation to encrypt respective plaintext inputs having a number of bytes. At least two bytes of a plaintext input have values based on a respective set of bits of a plurality of sets of bits of an initialization vector, wherein individual bits of the respective set of bits are introduced into respective individual bytes of the plaintext input and the respective set of bits has at least two bits and at most a number of bits equal to the number of bytes of the plaintext input.
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10.发明授权公开(公告)号：US12204092B2
公开(公告)日：2025-01-21
申请号：US17480634
申请日：2021-09-21
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Del Sarto , Alex Gritti , Amedeo Maierna , Luca Maggi
Abstract: An electronic module includes a first die of semiconductor material including a first reflector, a second die of semiconductor material including a second reflector, and a frame including a first supporting portion and a second supporting portion parallel to one another. The first and second dies are carried, respectively, by the first and second supporting portions and are respectively arranged so that the first reflector faces the second supporting portion and the second reflector faces the first supporting portion. An incoming light beam impinges upon the first reflector and is reflected on the second reflector so as to be supplied at output from the electronic module.
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