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公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
Inventor： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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2.发明授权公开(公告)号：US11256442B2
公开(公告)日：2022-02-22
申请号：US17087070
申请日：2020-11-02
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni
IPC: G06F3/06
Abstract: A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.
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公开(公告)号：US20210183442A1
公开(公告)日：2021-06-17
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
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公开(公告)号：US20210125668A1
公开(公告)日：2021-04-29
申请号：US17072887
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti
IPC: G11C13/00
Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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公开(公告)号：US10901919B2
公开(公告)日：2021-01-26
申请号：US16455155
申请日：2019-06-27
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Federico Goller , Michele Febbrarino
Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10824417B2
公开(公告)日：2020-11-03
申请号：US16225557
申请日：2018-12-19
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni
Abstract: A method for management of a differential memory includes storing first logic data associated with a first informative content in an auxiliary memory module of the differential memory; storing third logic data associated with a second informative content in a second submodule of a main memory module by overwriting second logic data associated with the first informative content while maintaining the first logic data contained in a first submodule of the main memory module unaltered; when the third logic data is being stored, reading the first logic data from the auxiliary memory module in a single-ended mode in response to a request for reading the first informative content; otherwise, reading the first logic data from the first submodule; and reading the third logic data in single-ended mode.
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公开(公告)号：US10522220B2
公开(公告)日：2019-12-31
申请号：US16056818
申请日：2018-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfre′
Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.
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公开(公告)号：US20190051348A1
公开(公告)日：2019-02-14
申请号：US16056818
申请日：2018-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfre'
IPC: G11C13/00
Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.
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公开(公告)号：US10115460B2
公开(公告)日：2018-10-30
申请号：US15639540
申请日：2017-06-30
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfre′ , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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10.发明申请公开(公告)号：US20170213580A1
公开(公告)日：2017-07-27
申请号：US15477695
申请日：2017-04-03
Applicant: STMicroelectronics S.r.l
Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.
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