公开(公告)号：US20250077240A1

公开(公告)日：2025-03-06

申请号：US18949686

申请日：2024-11-15

Applicant: STMicroelectronics (Grand Ouest) SAS ,  STMicroelectronics France

Inventor： Frederic RUELLE ,  Laurent MEUNIER ,  Bechir JABRI ,  Emmanuel GRANDIN ,  Nabil SAFI ,  Ghaith OUESLATI ,  Yohann MARTINIAULT ,  Jerome CAILLET

IPC: G06F9/445 ,  G06F3/0482 ,  G06F9/4401 ,  G06F9/451

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

公开(公告)号：US12210758B2

公开(公告)日：2025-01-28

申请号：US17733779

申请日：2022-04-29

Applicant: STMicroelectronics France

Inventor： Zouhaier Aouaini ,  Haithem Rahmani

IPC: G06F3/06 ,  G06F16/18

Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.

公开(公告)号：US12184289B2

公开(公告)日：2024-12-31

申请号：US18492597

申请日：2023-10-23

Applicant: STMicroelectronics France

Inventor： Lionel Vogt

IPC: H03K5/00

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

公开(公告)号：US12039293B2

公开(公告)日：2024-07-16

申请号：US17961927

申请日：2022-10-07

Applicant: STMicroelectronics France

Inventor： Tarek Bochkati

IPC: G06F8/30

CPC classification number: G06F8/30

Abstract: System, method, and circuitry for generating a linker model for use by a toolchain associated with a programmable computing device. One or more regions in the memory resources available to the programmable computing devices is defined for used by an application executing on the programmable computing device. One or more sections is defined for those regions for use by the application. Resource boundaries are generated for the application based on the defined regions and the defined sections. A user is enabled to modify the defined regions or the defined sections or the generated resource boundaries. A linker model is then generated based on the available memory resources, the defined regions, the defined sections, and the generated resource boundaries. This linker model is then utilized to generate a linker script for the programmable computing device based the linker syntax compatible with a toolchain linker for the programmable computing device.

公开(公告)号：US20240213153A1

公开(公告)日：2024-06-27

申请号：US18541497

申请日：2023-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V. ,  STMicroelectronics France

Inventor： Olivier Weber ,  Rohit Kumar Gupta ,  Eric Vandenbossche

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0928 ,  H01L23/528 ,  H01L27/0207

Abstract: An electronic device including a first active area of a first transistor, a first insulating region forming a first insulation of the first active area, a first insulating gate extending above the first active area and forming a second insulation of the first active area, and a first insulating gate contact coupled to the first insulating gate and positioned above both the first active area and the first insulating region, wherein the first insulating gate contact couples the first insulating gate to a power supply rail.

公开(公告)号：US20240178817A1

公开(公告)日：2024-05-30

申请号：US18520167

申请日：2023-11-27

Applicant: STMicroelectronics France

Inventor： Eric Andre ,  Lionel Vogt

IPC: H03H11/04 ,  H03K3/037 ,  H03K17/687 ,  H04B1/04

CPC classification number: H03H11/04 ,  H03K3/037 ,  H03K17/6871 ,  H04B1/04

Abstract: In embodiments, a radio frequency transmitter comprising at least one filtering circuit is provided. The filtering circuit includes a series/parallel shift register comprising a binary input and N binary outputs, with N being an integer greater than or equal to OSR, OSR being an integer greater than or equal to 2. The binary outputs ranging from 0 to N−1, the register receiving a binary data signal at a data frequency on its input and implementing shifts on the N binary outputs at a frequency equal to a multiplier of the data frequency and OSR. The filtering circuit further comprising a first circuit defined by N coefficients Ci. For each non-zero coefficient Ci, a signal determined by the coefficient Ci and by the corresponding one of the binary outputs. The filtering circuit further comprising and an adder circuit delivering an output equal to the sum of analog signals.

公开(公告)号：US20240143987A1

公开(公告)日：2024-05-02

申请号：US18382638

申请日：2023-10-23

Applicant: STMicroelectronics FRANCE ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Vincent HEINRICH ,  Pascal URARD ,  Bruno PAILLE

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: An integrated circuit includes a computer unit configured to execute the neural network. Parameters of the neural network are stored in a first memory. Data supplied at the input of the neural network or generated by the neural network are stored in a second memory. A first barrel shifter circuit transmits data from the second memory to the computer unit. A second barrel shifter circuit delivers data generated during the execution of the neural network by the computer unit to the second memory. A control unit is configured to control the computer unit, the first and second barrel shifter circuits, and accesses to the first memory and to the second memory.

公开(公告)号：US11894382B2

公开(公告)日：2024-02-06

申请号：US17544665

申请日：2021-12-07

Applicant: STMicroelectronics France ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier Weber ,  Christophe Lecocq

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

公开(公告)号：US12249991B2

公开(公告)日：2025-03-11

申请号：US18345726

申请日：2023-06-30

Applicant: STMicroelectronics France

Inventor： Laurent Jean Garcia ,  Marc Houdebine

IPC: H03K3/03 ,  H03K5/1252

Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.

公开(公告)号：US20240413228A1

公开(公告)日：2024-12-12

申请号：US18809567

申请日：2024-08-20

Applicant: STMicroelectronics France

Inventor： Philippe GALY

IPC: H01L29/739 ,  H10B41/40

Abstract: A cell includes a Z-PET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.