Abstract:
Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or the entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.
Abstract:
An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.
Abstract:
Techniques to detect whether or not a remote terminal is under the coverage of a repeater within a wireless communication network, which may be based on (1) a list of base stations expected to be received while under the repeater's coverage, (2) the characterized environment of the repeater, and/or (3) the propagation delays for a transmission received at the remote terminal. Additional ambiguity resulting from being under a repeater's coverage may also be accounted for and/or compensated by (1) discarding time measurements from repeated base stations, (2) adjusting the processing for position estimation to account for the additional ambiguity due to the repeater, (3) computing a series of position estimates based on multiple transmissions received from the same originating base station and selecting the best estimate, and/or (4) computing a series of position estimates based on multiple transmissions from multiple originating base stations and selecting the best estimate.
Abstract:
A method and apparatus for calibrating a Base Station and Mobile Station for use in systems that use round trip delay and systems that do not use round trip delay.
Abstract:
A system and method for providing timing information to a wireless device in a position determination system is disclosed. A wireless device includes a reference signal receiver, a signal processor, a wireless communications transceiver and a GPS receiver. The wireless device is adapted to receive a reference signal, extract a snippet of the received reference signal, determine a time of reception for the snippet and transmit the snippet and time of reception to a position determination entity as part of a request for GPS aiding information. The position determination entity includes a timing source, a GPS memory for storing GPS satellite information, a reference signal memory, a communications interface, a signal processor and a control processor. The position determination entity is adapted to continually receive and store a reference signal along with an associated time of reception, and receive the snippet and timestamp transmitted from the wireless device. The position determination entity is further adapted to match the signal snippet to a portion of the stored reference signal, determine a time offset between the timestamp and the time of reception of the matched portion of the stored reference signal, prepare aiding information for the wireless device, synchronize the aiding information to the wireless device using the time offset, and transmit the synchronized aiding information to the wireless device. The wireless device is further adapted to receive the aiding information, including timing information to assist the wireless device in acquiring the GPS signals.
Abstract:
A system and method for providing timing information to a wireless device in a position determination system is disclosed. A wireless device includes a reference signal receiver, a signal processor, a wireless communications transceiver and a GPS receiver. The wireless device is adapted to receive a reference signal, extract a snippet of the received reference signal, determine a time of reception for the snippet and transmit the snippet and time of reception to a position determination entity as part of a request for GPS aiding information. The position determination entity includes a timing source, a GPS memory for storing GPS satellite information, a reference signal memory, a communications interface, a signal processor and a control processor. The position determination entity is adapted to continually receive and store a reference signal along with an associated time of reception, and receive the snippet and timestamp transmitted from the wireless device. The position determination entity is further adapted to match the signal snippet to a portion of the stored reference signal, determine a time offset between the timestamp and the time of reception of the matched portion of the stored reference signal, prepare aiding information for the wireless device, synchronize the aiding information to the wireless device using the time offset, and transmit the synchronized aiding information to the wireless device. The wireless device is further adapted to receive the aiding information, including timing information to assist the wireless device in acquiring the GPS signals.
Abstract:
A method and system for disabling a mobile unit to handle a call processing function, after being away from its charging unit longer than a predetermined time period, allows a service provider to limit the mobility of the mobile unit with respect to its companion charging unit. Consequently, the service provider may limit the mobility of the mobile unit in a limited area, such as in a wireless local loop.
Abstract:
A system and method provide aiding information to a wireless device. The wireless device extracts a snippet of a received reference signal, generates a timestamp representing the time of reception thereof, and transmits the snippet and timestamp to a position determination entity (PDE). The PDE receives and stores a reference signal along with its reception time, and receive the snippet and timestamp from the wireless device. The PDE matches the snippet to a portion of the stored reference signal, and determines a time offset between the timestamp and the time of reception of the matched portion of the stored reference signal, The PDE then prepares the aiding information, synchronizes it to the wireless device using the time offset, and transmits the synchronized aiding information to the wireless device.
Abstract:
In a pipelined logic circuit, switches are only enabled when voltage differentials across the switches are zero. The switches are configured during a restored state of voltage rails, and a swing in voltage on the rails results in a swing in output voltage to a set level. To restore the logic circuit with minimal energy dissipation and permit useful pipelining, the inputs are regenerated through an inverse logic circuit. The voltage rail then swings back to its restored level. Full forward and reverse pipelines are formed with the individual forward and inverse logic circuits with the pipelines being driven by multiphase clock rails. Each logic stage includes a logic gate and a pass gate.