公开(公告)号：US07920592B2

公开(公告)日：2011-04-05

申请号：US11642238

申请日：2006-12-20

Applicant: Chia Sheng Lu ,  Sam Chu

Inventor： Chia Sheng Lu ,  Sam Chu

IPC: H04J3/16 ,  H04J3/18

CPC classification number: H04L47/522 ,  H04L47/24 ,  H04L47/50 ,  H04L47/527

Abstract: A method of bandwidth control and a corresponding bandwidth control device are disclosed, in which a plurality of queues are provided, bandwidth is assigned to each of the queues on the basis of a strict priority scheme, and additional bandwidth is assigned to the queues on the basis of a fair queuing scheme.

Abstract translation: 公开了一种带宽控制方法和相应的带宽控制装置，其中提供多个队列，基于严格优先级方案，将带宽分配给每个队列，并且将附加带宽分配给队列 公平排队计划的基础。

公开(公告)号：US20080151920A1

公开(公告)日：2008-06-26

申请号：US11642238

申请日：2006-12-20

Applicant: Chia Sheng Lu ,  Sam Chu

Inventor： Chia Sheng Lu ,  Sam Chu

IPC: H04L12/56

CPC classification number: H04L47/522 ,  H04L47/24 ,  H04L47/50 ,  H04L47/527

Abstract: A method of bandwidth control and a corresponding bandwidth control device are disclosed, in which a plurality of queues are provided, bandwidth is assigned to each of the queues on the basis of a strict priority scheme, and additional bandwidth is assigned to the queues on the basis of a fair queuing scheme.

Abstract translation: 公开了一种带宽控制方法和相应的带宽控制装置，其中提供多个队列，基于严格优先级方案，将带宽分配给每个队列，并且将附加带宽分配给队列 公平排队计划的基础。

公开(公告)号：US20050099851A1

公开(公告)日：2005-05-12

申请号：US10703017

申请日：2003-11-06

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: G11C7/10 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1012 ,  G11C7/1051 ,  G11C8/10

Abstract: A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.

Abstract translation: 位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。 各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。 选择器处于耦合到相应输出节点的Q组中。 每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。 第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。 第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。 用于N + 1个多路复用器的输出逻辑门分别​​具有分别耦合到R个节点的R个输入。 多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。

公开(公告)号：US20070229132A1

公开(公告)日：2007-10-04

申请号：US11277691

申请日：2006-03-28

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: H03K3/00

CPC classification number: H03K3/0375 ,  G01R31/318533 ,  G01R31/318536 ,  H03K3/013 ,  H03K3/356121 ,  H03K19/00392

Abstract: A latch is described that provides soft error rate protection with integrated scan capability and collision avoidance. The latch has a latch output node and a first, second, and third sublatches. Each sublatch has a respective input circuitry, output node, and feedback circuitry coupled to the output node for reinforcing an output signal of the sublatch. Each sublatch is operable to receive a data signal at its input circuitry and responsively generate a binary-state output signal on its output nodes. The first and second output nodes such that, if an output of the third sublatch changes, the first and second sublatches force the third sublatch to have a same output. This “forced” change reduces the soft error rate in the latch and the output signal of the latch output node is restored without the sublatches colliding.

Abstract translation: 描述了提供具有集成扫描能力和避免碰撞的软错误率保护的锁存器。 闩锁具有闩锁输出节点和第一，第二和第三子实体。 每个分支具有相应的输入电路，输出节点和耦合到输出节点的反馈电路，用于加强子锁的输出信号。 每个子选项可操作以在其输入电路处接收数据信号，并在其输出节点上响应地生成二进制状态输出信号。 第一和第二输出节点使得如果第三个分支的输出发生变化，则第一和第二个分页强制第三个分块具有相同的输出。 这种“强制”改变降低了锁存器中的软错误率，并且恢复锁存器输出节点的输出信号，而不会使得副本碰撞。

公开(公告)号：US20060039203A1

公开(公告)日：2006-02-23

申请号：US10922247

申请日：2004-08-19

Applicant: Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

Inventor： Sam Chu ,  Peter Klim ,  Michael Lee ,  Jose Paredes

IPC: G11C7/10

CPC classification number: G11C7/22

Abstract: A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

Abstract translation: 使用检测单元结合读写后阻塞的寄存器文件装置和方法在高性能寄存器文件中提供改进的读访问时间。 一个或多个与寄存器文件单元相同并且位于寄存器文件阵列中的检测单元用于通过将检测单元配置为在写入时的交替值或在写入之后变为特定值来控制寄存器文件中的读取操作 然后通过检测有源检测单元的状态变化来检测写入是否已经完成。 状态改变检测可以用于延迟读选通脉冲的前沿，或者可以在访问控制逻辑中使用以延迟下一个读选通脉冲的产生。 寄存器文件因此提供了一种可扩展的设计，不需要针对每个应用进行调整，并且跟踪过电压和时钟偏移变化。

公开(公告)号：US20050216698A1

公开(公告)日：2005-09-29

申请号：US10798902

申请日：2004-03-11

Applicant: Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

Inventor： Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

IPC: G06F9/30 ,  G06F15/00

CPC classification number: G06F9/30141

Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Abstract translation: 集成电路中经常使用寄存器文件来临时保存数据。 有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。 传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。 然而，多路复用器插入在高性能集成电路中不期望的延迟。 多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。

公开(公告)号：US20050083774A1

公开(公告)日：2005-04-21

申请号：US10687238

申请日：2003-10-16

Applicant: Tai Cao ,  Sam Chu ,  Joseph McGill ,  Michael Vaden

Inventor： Tai Cao ,  Sam Chu ,  Joseph McGill ,  Michael Vaden

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/18 ,  G11C8/00

CPC classification number: G11C7/109 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/225 ,  G11C8/08 ,  G11C8/18

Abstract: A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.

Abstract translation: 存储器阵列包括存储单元，其具有多个部分和解码器，所述部分和解码器耦合到相应的部分，用于对N位地址信号进行解码，并响应地确定由地址信号选择的一条字线上的信号。 本地时钟缓冲器耦合到解码器中的相应解码器，用于接收时钟信号和包括N位地址信号的M个最高有效位的地址信号并产生相应的定时信号。 解码器从其各自的本地时钟缓冲器接收定时信号。 每个解码器可操作以响应于定时信号的相位交替地预充电和评估N位地址信号。 每个本地时钟缓冲器可操作地响应于地址信号的M位的状态，用于在保持其定时信号处于无效状态并使其定时信号跟随时钟信号之间进行选择。

公开(公告)号：US5519239A

公开(公告)日：1996-05-21

申请号：US336886

申请日：1994-11-10

Applicant: Sam Chu

Inventor： Sam Chu

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L29/45 ,  H01L29/76

CPC classification number: H01L27/11526 ,  H01L27/10844 ,  H01L27/11546 ,  H01L29/456 ,  Y10S257/905

Abstract: A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer to a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation. In this manner, the self-formed contact allows for significant size reduction of the contact pitch. Moreover, using other plugs to form the self-aligned source lines of the array further reduces the size of the word line pitch, thereby dramatically reducing the associated cell size and allowing formation of ultra-high density memory arrays.

Abstract translation: 提供了一种结构和方法，其通过在阵列中形成自形成接触和自对准源极线来减小存储单元尺寸。 在本发明的一个实施例中，阵列形成多个存储单元。 然后，将第一绝缘层沉积在阵列上，随后蚀刻以在每个存储单元的侧壁上形成间隔物。 然后在相邻间隔件之间形成导电塞。 随后，在阵列上沉积第二绝缘层。 最后，通过第二绝缘层形成漏极触点到第一组插头。 其他插头形成阵列的源线。 因为本发明提供自形成的接触，所以仅蚀刻第二绝缘层以建立金属位线与下面的扩散漏极区之间的接触。 因此，本发明确保每个存储单元的适当隔离，同时减少接触形成所需的面积。 以这种方式，自形成接触允许接触间距的显着尺寸减小。 此外，使用其他插头来形成阵列的自对准源极线进一步减小了字线间距的大小，从而显着地减小了相关的单元尺寸并允许形成超高密度存储器阵列。

公开(公告)号：US20070240023A1

公开(公告)日：2007-10-11

申请号：US11278439

申请日：2006-04-03

Applicant: Vikas Agarwal ,  Sam Chu ,  Hung Le

Inventor： Vikas Agarwal ,  Sam Chu ,  Hung Le

IPC: G01R31/28

CPC classification number: G01R31/318541

Abstract: A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as loading cells by means of scanning input in a series through a low order cell to a higher order cell. The circuit may be copied as a series of cells wherein a bit held in each first-type cell is copied to the next higher second-type cell.

Abstract translation: 电路允许用户呈现信号以控制从第一型电池到第二型电池的数据流。 电路容易单独加载每个单元，以及通过将低阶单元的串行扫描输入到高阶单元来加载单元。 电路可以被复制为一系列单元，其中保持在每个第一类型单元中的位复制到下一较高的第二类型单元。

公开(公告)号：US20070171757A1

公开(公告)日：2007-07-26

申请号：US11340535

申请日：2006-01-26

Applicant: Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

Inventor： Michael Lee ,  Jose Paredes ,  Peter Klim ,  Sam Chu

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

Abstract translation: 一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及M位行驱动器装置116，响应于M行104中的每一个的均匀字数据位，以禁止均匀字数据位为第一值的M行104的通电。