公开(公告)号：US07983085B2

公开(公告)日：2011-07-19

申请号：US12367097

申请日：2009-02-06

Applicant: Satoru Tamada

Inventor： Satoru Tamada

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.

Abstract translation: 至少一个数据线对具有与第一列存储器单元对准的第一数据线和与第二列存储器单元对准的第二数据线。 第一数据线耦合到第二列存储器单元，并且第二数据线耦合到第一列存储器单元。

公开(公告)号：US20060158932A1

公开(公告)日：2006-07-20

申请号：US11329036

申请日：2006-01-11

Applicant: Satoru Tamada ,  Yuichi Kunori ,  Fumihiko Nitta

Inventor： Satoru Tamada ,  Yuichi Kunori ,  Fumihiko Nitta

IPC: G11C16/06

CPC classification number: G11C16/26

Abstract: A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.

Abstract translation: 具有低阈值电压的虚拟单元被布置在与存储单元对准的存储单元阵列中。 选择与所选存储单元列相邻的具有低阈值电压的虚拟单元，并且所选择的存储单元的源极局部位线通过这样的虚设单元耦合到全局位线。 由于源极本地位线在其两端耦合到接地节点，所以可以减小存储器单元的源极电阻，并且存储单元的源极电阻对存储单元阵列内的位置的依赖性也可以是 减少 这允许减小存储器单元的源电阻对存储单元阵列内的位置和非易失性半导体存储器件中的温度的依赖性。

公开(公告)号：US06519186B2

公开(公告)日：2003-02-11

申请号：US09822365

申请日：2001-04-02

Applicant: Satoru Tamada ,  Hidenori Mitani

Inventor： Satoru Tamada ,  Hidenori Mitani

IPC: G11C1604

CPC classification number: G11C11/5628 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0416

Abstract: A non-volatile semiconductor memory device includes, a plurality of word lines, a plurality of bit lines, a plurality of memory circuits, and a reading circuit. A plurality of bits are memorized at each memory cell. The plurality of bit lines lie at right angle to the word lines. The reading circuit is configured to read certain data from every (n−1)th (n is an integer that is greater than two) memory cell of a memory cell array that is connecting to at least a word line. The memory cell exists on the point of intersection with the word line and the bit line. Then data reading and data writing are made by applying the voltage on the word line and the bit line. The non-volatile semiconductor memory device is electrically rewritable.

Abstract translation: 非易失性半导体存储器件包括多个字线，多个位线，多个存储器电路和读取电路。 多个比特存储在每个存储单元中。 多个位线与字线成直角。 读取电路被配置为从至少连接到字线的存储单元阵列的每个（n-1）th（n是大于2的整数）存储单元读取某些数据。 存储单元存在于与字线和位线的交点上。 然后通过在字线和位线上施加电压来进行数据读取和数据写入。 非易失性半导体存储器件是电可重写的。

公开(公告)号：US08576627B2

公开(公告)日：2013-11-05

申请号：US13178278

申请日：2011-07-07

Applicant: Satoru Tamada

Inventor： Satoru Tamada

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.

Abstract translation: 至少一个数据线对具有与第一列存储器单元对准的第一数据线和与第二列存储器单元对准的第二数据线。 第一数据线耦合到第二列存储器单元，并且第二数据线耦合到第一列存储器单元。

公开(公告)号：US08422297B2

公开(公告)日：2013-04-16

申请号：US12981688

申请日：2010-12-30

Applicant: Satoru Tamada

Inventor： Satoru Tamada

IPC: G11C16/04 ,  G11C11/40

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C2211/5621

Abstract: Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.

Abstract translation: 公开了存储器件和方法以便于利用多电平抑制编程方案。 在一个这样的实施例中，具有升高的通道偏置电平的隔离沟道区域跨越多个存储器单元形成，并且部分地产生并通过与耦合到存储器单元并被偏置到预定偏置电平的字线的电容耦合来维持。 还公开了通过施加的影响程序抑制效果的字线偏置电压来操纵隔离沟道区域偏置电平的方法。

公开(公告)号：US20120063226A1

公开(公告)日：2012-03-15

申请号：US13302050

申请日：2011-11-22

Applicant: Tetsuji Manabe ,  Satoru Tamada

Inventor： Tetsuji Manabe ,  Satoru Tamada

IPC: G11C16/26 ,  G11C29/00

CPC classification number: G11C16/349 ,  G11C16/04 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409

Abstract: Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected data is loaded into a second data cache. After a read operation of programmed columns of memory cells, the read data is compared to the expected data and error bit indicators are stored in the second data cache in the error bit locations. The second data cache is masked with the mask data so that only those error bits that are unmasked are counted. If the number of unmasked error bit indicators is greater than a threshold, the memory block is marked as unusable.

Abstract translation: 公开了小单元内部验证读取操作的方法和存储器件。 在一种这样的方法中，期望的数据被编程成存储器单元的列的分组（例如，存储器块）。 掩模数据被加载到三个动态数据高速缓存的第三动态数据高速缓存中。 预期数据被加载到第二数据高速缓存中。 在对存储器单元的编程列的读取操作之后，将读取的数据与预期数据进行比较，并且错误位指示器存储在错误位置中的第二数据高速缓存中。 第二个数据高速缓存用掩码数据进行掩码，以便仅对未被屏蔽的错误位进行计数。 如果未屏蔽的错误位指示器的数量大于阈值，则内存块被标记为不可用。

公开(公告)号：US20110096599A1

公开(公告)日：2011-04-28

申请号：US12981688

申请日：2010-12-30

Applicant: Satoru Tamada

Inventor： Satoru Tamada

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C2211/5621

Abstract: Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.

Abstract translation: 公开了存储器件和方法以便于利用多电平抑制编程方案。 在一个这样的实施例中，具有升高的通道偏置电平的隔离沟道区域跨越多个存储器单元形成，并且部分地产生并通过与耦合到存储器单元并被偏置到预定偏置电平的字线的电容耦合来维持。 还公开了通过施加的影响程序抑制效果的字线偏置电压来操纵隔离沟道区域偏置电平的方法。

公开(公告)号：US20100149866A1

公开(公告)日：2010-06-17

申请号：US12705917

申请日：2010-02-15

Applicant: Satoru Tamada

Inventor： Satoru Tamada

IPC: G11C16/04

CPC classification number: G11C16/3418

Abstract: Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of conductors disposed on both a source side and a drain side of a floating-gate transistor, wherein a source side of the first pulse pattern has a different median voltage than a drain side of the first pulse pattern.

Abstract translation: 公开了方法，系统和设备，一种这样的设备是被配置为通过布置在浮栅晶体管的源极侧和漏极侧的多个导体同时断言第一脉冲图案的存储器件，其中源极侧 第一脉冲图案具有与第一脉冲图案的漏极侧不同的中间电压。

公开(公告)号：US06744670B2

公开(公告)日：2004-06-01

申请号：US10315034

申请日：2002-12-10

Applicant: Satoru Tamada ,  Tatsuya Saeki

Inventor： Satoru Tamada ,  Tatsuya Saeki

IPC: G11C1604

CPC classification number: G11C16/349 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10

Abstract: The number of times of rewriting of memory cells is stored by number of rewrite (EW) times storage section. In data rewriting to memory cells, number of rewriting times data of a selected memory cell is transferred to and latched in a number of EW times sense latch section and transferred to a number of EW times counter. Controlling processor (CPU) sets a condition on a write pulse on the basis of a value obtained by updating a count value of the number of EW times counter and controls the operation of rewriting. In data rewriting, a count value after update of the number of EW times counter is transferred to the number of EW times sense latch section. The updated number of rewritings is transferred to a corresponding number of EW times storage section, in parallel to data rewriting to a memory cell.

Abstract translation: 通过重写（EW）次存储部分存储存储器单元的重写次数。 在对存储器单元的数据重写中，所选择的存储单元的重写次数数据被传送到并被锁存在多个EW次检测锁存部分中并被转移到多个EW次计数器。 控制处理器（CPU）基于通过更新EW次数计数器的计数值而获得的值来设置写入脉冲上的条件，并控制重写操作。 在数据重写中，更新EW次数计数器之后的计数值被转移到EW次检测锁存部分的数量。 将更新的重写次数与数据重写到存储器单元并行地传送到相应数量的EW次存储部分。

公开(公告)号：US06396738B1

公开(公告)日：2002-05-28

申请号：US09805044

申请日：2001-03-14

Applicant: Satoru Tamada ,  Tatsuya Saeki

Inventor： Satoru Tamada ,  Tatsuya Saeki

IPC: G11C1604

CPC classification number: G11C16/3459 ,  G11C16/3454

Abstract: There is provided a non-volatile semiconductor device having a memory cell in which a threshold value voltage changes in accordance with the application of the writing pulse having a predetermined width and voltage with respect to word lines and bit lines and data depending upon the threshold value voltage is written, wherein writing failure is generated in the first time data writing operation, and a writing condition is set for suppressing the writing condition is set which is capable of suppressing the writing failure rate than the case of the first time writing operation when the writing operation is re-executed.

Abstract translation: 提供了一种具有存储单元的非易失性半导体器件，其中阈值电压根据具有相对于字线和位线的预定宽度和电压的写入脉冲的应用而改变，并且取决于阈值 写入电压，其中在第一次数据写入操作中产生写入失败，并且设置用于抑制写入条件的写入条件，该写入条件被设置为与第一次写入操作的情况相比能够抑制写入失败率 写操作被重新执行。