公开(公告)号：US07533253B2

公开(公告)日：2009-05-12

申请号：US11025091

申请日：2004-12-28

申请人： Seong-Kue Jo

发明人： Seong-Kue Jo

IPC分类号： G06F9/00 ,  G06F15/177

CPC分类号： G06F9/4403

摘要： A multi-chip system and a boot code fetch method include a nonvolatile memory chip storing a volatile memory chip, and a boot code, and a host fetching the boot code. The boot code is transferred to the volatile memory chip before the host fetches the boot code in the nonvolatile memory chip, and the boot code is fetched in the volatile memory chip. Therefore, a bootRAM of the conventional nonvolatile memory chip may be removed, so that an area of the nonvolatile memory chip can be reduced.

摘要翻译： 多芯片系统和引导代码提取方法包括存储易失性存储器芯片的非易失性存储器芯片和引导代码以及取得引导代码的主机。 在主机在非易失性存储器芯片中取出引导代码之前，引导代码被传送到易失性存储器芯片，引导代码被取出在易失性存储器芯片中。 因此，可以去除传统的非易失性存储器芯片的引导RAM，从而可以减小非易失性存储器芯片的面积。

公开(公告)号：US20090046533A1

公开(公告)日：2009-02-19

申请号：US11665635

申请日：2005-07-26

申请人： Seong-Kue Jo

发明人： Seong-Kue Jo

IPC分类号： G11C8/00

CPC分类号： G06F13/1694

摘要： Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data to the second memory chip in response to local transfer information provided from the host system. The first memory chip controls the host system not to access the first and second memory chips while conducting a local transfer operation. According to the invention, since the data is able to be directly transferred between the memory chips without the host system, it enhances the efficiency of the multichip system and improves a data transfer speed.

摘要翻译： 公开了一种直接在存储器芯片之间传送数据的多芯片系统和方法。 多芯片系统包括第一和第二存储器芯片以及用于控制第一和第二存储器芯片的操作的主机系统。 响应于从主机系统提供的本地传送信息，第一存储器芯片控制第二存储器芯片将数据传送到第二存储器芯片。 第一存储器芯片控制主机系统在进行本地传送操作时不访问第一和第二存储器芯片。 根据本发明，由于数据能够在没有主机系统的情况下在存储器芯片之间直接传送，所以提高了多芯片系统的效率并提高了数据传输速度。

公开(公告)号：US07486570B2

公开(公告)日：2009-02-03

申请号：US11320975

申请日：2005-12-30

申请人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

发明人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

IPC分类号： G11C7/10

CPC分类号： G11C16/10

摘要： Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.

摘要翻译： 公开了一种闪存器件的程序方法，包括： 将数据存储在缓冲存储器中并产生高电压作为字线电压。 当数据传送到缓冲存储器完成时，程序方法将缓冲存储器中的数据同时传送到页缓冲电路，并根据字线电压对存储单元阵列中的页缓冲电路中的数据进行编程。

公开(公告)号：US07102927B2

公开(公告)日：2006-09-05

申请号：US10939197

申请日：2004-09-10

申请人： Seong-Kue Jo

发明人： Seong-Kue Jo

IPC分类号： G11C16/08 ,  G11C16/16

CPC分类号： G11C16/16

摘要： Methods are provided to program a memory device having a plurality of memory blocks. A first address for selecting a row of each of the memory blocks is generated according to a multi-page program operation. A second address for selecting a memory block is received and latched, which is repeated until second addresses of memory blocks to be selected are all received and latched. Memory blocks are selected by the latched second addresses, and then the same rows of the respective selected memory blocks are simultaneously activated according to the first address. Related memory devices also are described.

摘要翻译： 提供了用于对具有多个存储块的存储器件进行编程的方法。 根据多页程序操作生成用于选择每个存储块的行的第一地址。 接收并锁存用于选择存储器块的第二地址，其被重复直到所有被选择的存储器块的第二地址都被接收和锁存。 通过锁存的第二地址选择存储器块，然后根据第一地址同时激活相应选择的存储块的相同行。 还描述了相关的存储器件。

公开(公告)号：US06738282B2

公开(公告)日：2004-05-18

申请号：US10273947

申请日：2002-10-18

申请人： Seong-Kue Jo

发明人： Seong-Kue Jo

IPC分类号： G11C1124

CPC分类号： G11C7/06 ,  G11C7/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2207/065 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2211/4013

摘要： The disclosure is a method of controlling operations in a static random access memory employing twin cells. After a wordline coupled to first and second cell transistors is conductive, a voltage difference between a first bitline, which is connected to a first cell capacitor through the first cell transistor, and a second bitline, which is connected to a second cell capacitor through the second cell transistor, is driven into a sense amplifier to be developed with amplification. An active wordline turns nonconductive when one of the bitline voltages accords with a predetermined reference voltage.

摘要翻译： 本公开是一种控制采用双胞胎的静态随机存取存储器中的操作的方法。 在耦合到第一和第二单元晶体管的字线导通之后，通过第一单元晶体管连接到第一单元电容器的第一位线与通过第二单元电容器连接到第二单元电容器的第二位线之间的电压差 第二单元晶体管被驱动到读出放大器中以进行放大开发。 当其中一个位线电压符合预定参考电压时，有源字线变为不导通。

公开(公告)号：US06553520B1

公开(公告)日：2003-04-22

申请号：US09368035

申请日：1999-08-03

申请人： Seong-kue Jo

发明人： Seong-kue Jo

IPC分类号： G11C2900

CPC分类号： G11C29/08

摘要： An integrated circuit device includes a package and an externally accessible signal lead attached to the package. An integrated circuit chip is mounted in the package and connected to the signal lead. The integrated circuit chip includes a mode-selective signal generating circuit configured to receive a mode control signal and an internal signal and coupled to the externally accessible signal lead. The mode-selective signal generating circuit is operative to produce an output signal responsive to one of the internal signal or an external signal applied to the externally accessible signal lead based on the mode control signal. According to an embodiment, the integrated circuit chip further includes a memory circuit including a sense amplifier that senses a bit line voltage in response to a sense enable signal. The internal signal includes a sense enable control signal having a timing adapted for sensing a bit line voltage in a memory cycle of the memory circuit. The mode-selective signal generating circuit is operative to generate the sense enable signal responsive to one of the sense enable control signal or the external signal based on the mode control signal. In another embodiment, the internal signal includes an internally-generated reference signal produced at a reference signal bus, and the mode-selective signal generating circuit includes a transfer gate coupling the externally accessible signal lead to the reference voltage node and operative to apply a voltage applied to the externally accessible signal lead to the reference signal bus responsive to the mode control signal. Related operating methods are also provided.

摘要翻译： 集成电路器件包括一个封装和一个外部可访问的信号引线，连接到封装。 集成电路芯片安装在封装中并连接到信号引线。 集成电路芯片包括模式选择信号发生电路，其被配置为接收模式控制信号和内部信号并耦合到外部可访问的信号引线。 模式选择信号发生电路可操作以响应于内部信号之一或外部信号产生一个输出信号，该外部信号或外部信号基于模式控制信号。 根据实施例，集成电路芯片还包括存储电路，其包括响应于感测使能信号而感测位线电压的读出放大器。 内部信号包括具有适于感测存储器电路的存储器周期中的位线电压的定时的感测使能控制信号。 模式选择信号发生电路可操作以响应于基于模式控制信号的感测使能控制信号或外部信号之一产生感测使能信号。 在另一个实施例中，内部信号包括在参考信号总线处产生的内部产生的参考信号，并且模式选择信号产生电路包括将外部可访问的信号引线耦合到参考电压节点并且可操作地施加电压 响应于模式控制信号，施加到外部可访问信号导致参考信号总线。 还提供了相关的操作方法。

公开(公告)号：US07663924B2

公开(公告)日：2010-02-16

申请号：US11942331

申请日：2007-11-19

申请人： Jin-Kook Kim ,  Seong-Kue Jo

发明人： Jin-Kook Kim ,  Seong-Kue Jo

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C2216/14

摘要： Methods of programming a non-volatile memory device having at least one memory block with a plurality of memory cells located at intersections of rows and columns is disclosed. Pursuant to these methods, at least two addresses that select corresponding rows of the memory block may be received and temporarily stored. Then, the rows selected by the temporarily stored addresses may be simultaneously activated, and at least some of the memory cells in the activated rows are simultaneously programmed. Corresponding non-volatile memory devices are also provided.

摘要翻译： 公开了一种具有至少一个存储器块的非易失性存储器件的方法，其中多个存储单元位于行和列的交点处。 根据这些方法，可以接收并临时存储选择存储块的相应行的至少两个地址。 然后，可以同时激活由临时存储的地址选择的行，并且激活的行中的至少一些存储器单元被同时编程。 还提供了相应的非易失性存储器件。

公开(公告)号：US07327625B2

公开(公告)日：2008-02-05

申请号：US11194242

申请日：2005-08-01

申请人： Seong-Kue Jo

发明人： Seong-Kue Jo

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611

摘要： Methods for automatically refreshing a plurality of memory cells in a volatile memory device are provided in which an auto-refresh mode of the volatile memory device is activated in response to an auto-refresh mode activation command. Thereafter, an auto-refresh operation may be performed on the plurality of memory cells in response to an auto-refresh command. Related dynamic random access memory devices, memory systems and logic embedded memories are also provided.

摘要翻译： 提供了在易失性存储器件中自动刷新多个存储器单元的方法，其中响应于自动刷新模式激活命令来激活易失性存储器件的自动刷新模式。 此后，可以响应于自动刷新命令对多个存储器单元执行自动刷新操作。 还提供了相关的动态随机存取存储器件，存储器系统和逻辑嵌入式存储器。

公开(公告)号：US20070086243A1

公开(公告)日：2007-04-19

申请号：US11464454

申请日：2006-08-14

申请人： Seong-Kue JO

发明人： Seong-Kue JO

IPC分类号： G11C14/00

CPC分类号： G11C16/26 ,  G11C16/24

摘要： In a NOR-NAND flash memory device, data bits may be alternately selected from first and second mats. A selected wordline in a mat may be kept active until completing a read operation for data bits of more than one memory cells coupled to the selected wordline.

摘要翻译： 在NOR-NAND闪速存储器件中，可以从第一和第二垫交替地选择数据位。 垫中的所选字线可以保持有效，直到对耦合到所选字线的多于一个的存储器单元的数据位进行读操作。

公开(公告)号：US20060274582A1

公开(公告)日：2006-12-07

申请号：US11320975

申请日：2005-12-30

申请人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

发明人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

IPC分类号： G11C11/34

CPC分类号： G11C16/10

摘要： Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.