公开(公告)号：US10192782B2

公开(公告)日：2019-01-29

申请号：US14747316

申请日：2015-06-23

申请人： Woojin Lee ,  VietHa Nguyen ,  Wookyung You ,  Doo-Sung Yun ,  Hyunbae Lee ,  Byunghee Kim ,  Sang Hoon Ahn ,  Seungyong Yoo ,  Naein Lee ,  Hoyun Jeon

发明人： Woojin Lee ,  VietHa Nguyen ,  Wookyung You ,  Doo-Sung Yun ,  Hyunbae Lee ,  Byunghee Kim ,  Sang Hoon Ahn ,  Seungyong Yoo ,  Naein Lee ,  Hoyun Jeon

IPC分类号： H01L21/768 ,  H01L21/31 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213

摘要： A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

公开(公告)号：US20160133512A1

公开(公告)日：2016-05-12

申请号：US14747316

申请日：2015-06-23

申请人： Woojin LEE ,  VietHa NGUYEN ,  Wookyung YOU ,  Doo-Sung YUN ,  Hyunbae LEE ,  Byunghee KIM ,  Sang Hoon AHN ,  Seungyong YOO ,  Naein LEE ,  Hoyun JEON

发明人： Woojin LEE ,  VietHa NGUYEN ,  Wookyung YOU ,  Doo-Sung YUN ,  Hyunbae LEE ,  Byunghee KIM ,  Sang Hoon AHN ,  Seungyong YOO ,  Naein LEE ,  Hoyun JEON

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L21/31

CPC分类号： H01L21/76832 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76834

摘要： A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

摘要翻译： 制造半导体器件的方法包括提供具有导电图案的第一层间电介质层，在第一层间介质层上依次形成第一蚀刻停止层，第二蚀刻停止层，第二层间电介质层和掩模图案，形成 使用掩模图案作为掩模的第二层间电介质层中的开口，暴露第二蚀刻停止层的开口，以及执行蚀刻处理，包括同时去除由开口暴露的掩模图案和第二蚀刻停止层，以暴露第一蚀刻停止层 蚀刻停止层。