公开(公告)号：US09450428B2

公开(公告)日：2016-09-20

申请号：US14351321

申请日：2012-08-20

申请人： Hyeok-Hwi Na ,  Young-Seok Kim ,  Sang-Hoon Ahn ,  Sung-Beum Park ,  Seung-Wook Park ,  Hyun-Mok Cho ,  Sun-Bok Park ,  Jae-Goo Park ,  Ho-Suk Hwang

发明人： Hyeok-Hwi Na ,  Young-Seok Kim ,  Sang-Hoon Ahn ,  Sung-Beum Park ,  Seung-Wook Park ,  Hyun-Mok Cho ,  Sun-Bok Park ,  Jae-Goo Park ,  Ho-Suk Hwang

IPC分类号： H02J7/00 ,  H02H1/00 ,  H02H3/08 ,  H02H7/18 ,  H01M10/42 ,  H01M2/34 ,  H01M10/0525 ,  H01M2/02 ,  H01M2/04

CPC分类号： H02J7/0029 ,  H01L2224/48145 ,  H01L2224/49111 ,  H01L2924/19105 ,  H01M2/0217 ,  H01M2/0473 ,  H01M2/34 ,  H01M10/0525 ,  H01M10/4257 ,  H01M2010/4271 ,  H01M2200/00 ,  H01M2200/103 ,  H01M2200/106 ,  H02H1/0038 ,  H02H3/085 ,  H02H7/18 ,  Y02P70/54 ,  H01L2924/00012

摘要： Disclosed is a package module of a battery protection circuit. The package module comprises: a first internal connection terminal area and a second internal connection terminal area, and in which first and second internal connection terminals connected to a battery can provided with a bare cell are respectively disposed; an external connection terminal area, in which a plurality of external connection terminals are disposed; and a protection circuit area comprising a device area in which a plurality of passive devices forming the battery protection circuit are disposed and a chip area, which is adjacent to the device area, and in which a protection IC and a dual FET chip forming the battery protection circuit are disposed, are disposed between the external connection terminal area and the second internal connection terminal area.

摘要翻译： 公开了一种电池保护电路的封装模块。 封装模块包括：第一内部连接端子区域和第二内部连接端子区域，并且其中分别设置有连接到电池的第一和第二内部连接端子可以设置有裸电池; 设置有多个外部连接端子的外部连接端子区域; 以及保护电路区域，包括其中设置有形成电池保护电路的多个无源器件的器件区域和与器件区域相邻的芯片区域，并且其中形成电池的保护IC和双FET芯片 保护电路设置在外部连接端子区域和第二内部连接端子区域之间。

公开(公告)号：US08736018B2

公开(公告)日：2014-05-27

申请号：US13314575

申请日：2011-12-08

申请人： Kyoung-Hee Kim ,  Gil-Heyun Choi ,  Kyu-Hee Han ,  Byung-Lyul Park ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Kwang-Jin Moon

发明人： Kyoung-Hee Kim ,  Gil-Heyun Choi ,  Kyu-Hee Han ,  Byung-Lyul Park ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Kwang-Jin Moon

IPC分类号： H01L21/764 ,  H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/01327 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.

摘要翻译： 半导体器件包括具有第一触点的顶表面，具有第二触点的底表面，穿透基板的通孔，在通孔的侧壁上的绝缘层结构，其中具有气隙的绝缘层结构， 所述贯通电极在所述绝缘层结构上具有上表面和下表面，所述贯通电极填充所述通孔，所述下表面是所述第二接触，以及金属布线，电连接到所述通孔的上表面，并电连接到 第一次接触。

公开(公告)号：US20110263117A1

公开(公告)日：2011-10-27

申请号：US13094342

申请日：2011-04-26

申请人： Sang-Don Nam ,  Sang-Hoon Ahn ,  Byung-Hee Kim ,  Kyu-Hee Han

发明人： Sang-Don Nam ,  Sang-Hoon Ahn ,  Byung-Hee Kim ,  Kyu-Hee Han

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/2686 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76886 ,  H01L2221/1047

摘要： A method of manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device in which moisture is removed from a porous low-dielectric layer after a chemical mechanical polishing (CMP) process include formation of a porous low-dielectric layer on a substrate. A metal interconnection is formed on the substrate having the porous low-dielectric layer. The metal interconnection forms a planar surface with the porous low-dielectric layer to fill the openings. Ultraviolet (UV) light is irradiated to the porous low-dielectric layer to remove absorbed moisture from the porous low-dielectric layer. A capping layer is formed on the substrate having the porous low-dielectric layer and the metal interconnection. The capping layer is formed in-situ to prevent additional absorption of moisture.

摘要翻译： 制造半导体器件的方法和用于制造在化学机械抛光（CMP）工艺之后从多孔低电介质层去除水分的半导体器件的设备包括在衬底上形成多孔低电介质层。 在具有多孔低电介质层的基板上形成金属互连。 金属互连形成具有多孔低介电层的平坦表面以填充开口。 将紫外（UV）光照射到多孔低电介质层，以从多孔低介电层去除吸收的水分。 在具有多孔低电介质层和金属互连的基板上形成覆盖层。 封盖层原位形成以防止额外吸收水分。

公开(公告)号：US20110136332A1

公开(公告)日：2011-06-09

申请号：US12960150

申请日：2010-12-03

申请人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

发明人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC分类号： H01L21/28 ,  H01L21/31

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

摘要翻译： 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US07867924B2

公开(公告)日：2011-01-11

申请号：US12038278

申请日：2008-02-27

申请人： Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

发明人： Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76224 ,  H01L21/823481

摘要： A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

摘要翻译： 制造半导体器件的方法包括在下半导体衬底上形成下部器件，并在下部器件上形成层间绝缘膜。 在层间绝缘膜上形成上半导体衬底，使得层间绝缘膜位于下半导体衬底和上半导体衬底之间。 上沟槽形成在上半导体衬底内。 上部器件隔离膜形成在上部沟槽内。 用上述器件隔离膜中的杂质化学键的波长的紫外线照射上部器件隔离膜以降低其杂质浓度。

公开(公告)号：US20160163589A1

公开(公告)日：2016-06-09

申请号：US14955988

申请日：2015-12-01

申请人： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

发明人： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76807 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047

摘要： A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

摘要翻译： 形成半导体器件的方法可以包括使用具有选择为提供对后续蚀刻工艺的电阻的组成的材料形成绝缘层。 可以改变材料的组成以将材料的电阻降低到绝缘层中预定水平的后续蚀刻工艺。 可以在绝缘层上执行随后的蚀刻工艺，以将绝缘层的上部去除在预定水平以上，并且将绝缘层的下部分留在延伸穿过绝缘层的下部的相邻导电图案之间的预定水平以下 。 可以在相邻导电图案之间的绝缘层的下部上形成低k介电材料，以将绝缘层的上部替换为高于预定水平。

公开(公告)号：US20160133512A1

公开(公告)日：2016-05-12

申请号：US14747316

申请日：2015-06-23

申请人： Woojin LEE ,  VietHa NGUYEN ,  Wookyung YOU ,  Doo-Sung YUN ,  Hyunbae LEE ,  Byunghee KIM ,  Sang Hoon AHN ,  Seungyong YOO ,  Naein LEE ,  Hoyun JEON

发明人： Woojin LEE ,  VietHa NGUYEN ,  Wookyung YOU ,  Doo-Sung YUN ,  Hyunbae LEE ,  Byunghee KIM ,  Sang Hoon AHN ,  Seungyong YOO ,  Naein LEE ,  Hoyun JEON

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L21/31

CPC分类号： H01L21/76832 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76834

摘要： A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

摘要翻译： 制造半导体器件的方法包括提供具有导电图案的第一层间电介质层，在第一层间介质层上依次形成第一蚀刻停止层，第二蚀刻停止层，第二层间电介质层和掩模图案，形成 使用掩模图案作为掩模的第二层间电介质层中的开口，暴露第二蚀刻停止层的开口，以及执行蚀刻处理，包括同时去除由开口暴露的掩模图案和第二蚀刻停止层，以暴露第一蚀刻停止层 蚀刻停止层。

公开(公告)号：US08524615B2

公开(公告)日：2013-09-03

申请号：US13238297

申请日：2011-09-21

申请人： Sang-Hoon Ahn ,  Byung-Hee Kim ,  Sang-Don Nam ,  Kyu-Hee Han ,  Gil-heyun Choi ,  Jang-Hee Lee ,  Jong-Min Baek ,  Kyoung-Hee Kim

发明人： Sang-Hoon Ahn ,  Byung-Hee Kim ,  Sang-Don Nam ,  Kyu-Hee Han ,  Gil-heyun Choi ,  Jang-Hee Lee ,  Jong-Min Baek ,  Kyoung-Hee Kim

IPC分类号： H01L21/469 ,  H01L21/31 ,  H01L21/44

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/76829 ,  H01L2221/1047

摘要： Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.

摘要翻译： 示例性实施方案涉及形成硬化多孔介电层的方法。 该方法可以包括在衬底上形成含有致孔剂的电介质层，使用第一UV固化工艺将电介质层转化为多孔介电层，以从电介质层除去致孔剂，并将多孔电介质层转化成交联的多孔介电层 使用第二UV固化方法在多孔介电层中产生交联。

公开(公告)号：US08455985B2

公开(公告)日：2013-06-04

申请号：US13019520

申请日：2011-02-02

申请人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

发明人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

IPC分类号： H01L29/00

CPC分类号： H01L23/562 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L23/5258 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/04 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.

摘要翻译： 集成电路器件包括多个堆叠电路层，所述多个电路层中的至少一个包括复合层间绝缘层，所述复合层间绝缘层包括具有不同机械强度和介电特性的横向相邻的第一和第二绝缘材料区域，以及设置的多个电路部件 在复合层间绝缘层中。 第一绝缘材料区域可以具有比第二绝缘材料区域更低的介电常数和更低的机械强度，使得例如第一绝缘材料区域可以位于信号线附近或其他电路特征处以在使用第二绝缘材料区域时降低电容 绝缘材料区域靠近容易受到局部机械应力的位置，诸如熔断器位置，外部连接接合位置或划线位置。

公开(公告)号：US08367535B2

公开(公告)日：2013-02-05

申请号：US13053668

申请日：2011-03-22

申请人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

发明人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

IPC分类号： H01L21/28

CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881

摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

摘要翻译： 本文的示例性实施例涉及制造半导体器件的方法。 该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。 随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。 衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。 可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。