Abstract:
A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.
Abstract:
Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.