Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table
    1.
    发明授权
    Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table 有权
    使用可编程分支偏移表快速执行具有多个条件表达式的分支指令

    公开(公告)号:US08078849B2

    公开(公告)日:2011-12-13

    申请号:US12342851

    申请日:2008-12-23

    IPC分类号: G06F9/32

    摘要: Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.

    摘要翻译: 与本发明一致的方法和系统提供了可编程表,其允许软件定义多个分支功能,每个分支功能将条件代码的向量映射到分支偏移。 该技术允许灵活的多路分支功能,使用可由程序员指定的条件分支结果表。 任何指令都可以指定任意条件表达式的计算,以计算条件代码的值,并可以选择特定的分支函数。 当处理器执行指令时,处理器的算术/逻辑功能单元评估条件表达式,然后处理器根据指定的分支函数执行分支操作。

    Flow control systems and methods for multi-level buffering schemes
    2.
    发明授权
    Flow control systems and methods for multi-level buffering schemes 有权
    用于多级缓冲方案的流量控制系统和方法

    公开(公告)号:US07224691B1

    公开(公告)日:2007-05-29

    申请号:US10241759

    申请日:2002-09-12

    IPC分类号: H04L12/54

    摘要: A system receives data in multiple streams from an upstream device. The system temporarily stores the data in a first buffer and asserts a forward flow control signal when a capacity of the first buffer exceeds a first threshold value. The system reads the data from the first buffer and selectively processes the data based on the forward flow control signal. The system temporarily stores the selectively processed data in a number of second buffers, generates a backward flow control signal when a capacity of one of the second buffers exceeds a second threshold value, and sends the backward flow control signal to the upstream device.

    摘要翻译: 系统从上游设备接收多个流中的数据。 当第一缓冲器的容量超过第一阈值时,系统将数据临时存储在第一缓冲器中,并且断言正向流控制信号。 该系统从第一缓冲器读取数据,并根据前向流控制信号有选择地处理数据。 系统将选择处理的数据临时存储在多个第二缓冲器中,当第二缓冲器中的一个的容量超过第二阈值时产生反向流量控制信号,并将反向流量控制信号发送到上游装置。

    SCHEDULER FOR TRANSMIT SYSTEM INTERFACES
    4.
    发明申请
    SCHEDULER FOR TRANSMIT SYSTEM INTERFACES 有权
    发射系统接口的调度器

    公开(公告)号:US20100322243A1

    公开(公告)日:2010-12-23

    申请号:US12873187

    申请日:2010-08-31

    IPC分类号: H04L12/56

    摘要: A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the bursts is less than a size of a maximum burst associated with the data stream and schedules an additional burst in the data stream when the current burst size is less than the maximum burst size. The system transmits the current burst and the additional burst to balance bandwidth used by the data stream.

    摘要翻译: 系统平衡数据流使用的带宽。 系统接收数据流中的数据并将数据分割成突发。 系统然后识别突发中的当前一个的大小是否小于与数据流相关联的最大突发的大小,并且当当前突发大小小于最大突发大小时调度数据流中的附加突发。 系统发送当前突发和附加突发以平衡数据流使用的带宽。

    Scheduler for transmit system interfaces
    5.
    发明授权
    Scheduler for transmit system interfaces 失效
    传输系统接口调度器

    公开(公告)号:US07809853B1

    公开(公告)日:2010-10-05

    申请号:US11423311

    申请日:2006-06-09

    摘要: A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the bursts is less than a size of a maximum burst associated with the data stream and schedules an additional burst in the data stream when the current burst size is less than the maximum burst size. The system transmits the current burst and the additional burst to balance bandwidth used by the data stream.

    摘要翻译: 系统平衡数据流使用的带宽。 系统接收数据流中的数据并将数据分割成突发。 系统然后识别突发中的当前一个的大小是否小于与数据流相关联的最大突发的大小,并且当当前突发大小小于最大突发大小时调度数据流中的附加突发。 系统发送当前突发和附加突发以平衡数据流使用的带宽。

    Flow control systems and methods for multi-level buffering schemes
    7.
    发明授权
    Flow control systems and methods for multi-level buffering schemes 有权
    用于多级缓冲方案的流量控制系统和方法

    公开(公告)号:US07508831B1

    公开(公告)日:2009-03-24

    申请号:US11737489

    申请日:2007-04-19

    IPC分类号: H04L12/54

    摘要: A system receives data in multiple streams from an upstream device. The system temporarily stores the data in a first buffer and asserts a forward flow control signal when a capacity of the first buffer exceeds a first threshold value. The system reads the data from the first buffer and selectively processes the data based on the forward flow control signal. The system temporarily stores the selectively processed data in a number of second buffers, generates a backward flow control signal when a capacity of one of the second buffers exceeds a second threshold value, and sends the backward flow control signal to the upstream device.

    摘要翻译: 系统从上游设备接收多个流中的数据。 当第一缓冲器的容量超过第一阈值时,系统将数据临时存储在第一缓冲器中,并且断言正向流控制信号。 该系统从第一缓冲器读取数据,并根据前向流控制信号有选择地处理数据。 系统将选择处理的数据临时存储在多个第二缓冲器中,当第二缓冲器中的一个的容量超过第二阈值时产生反向流量控制信号,并将反向流量控制信号发送到上游装置。

    Local stall control method and structure in a microprocessor
    8.
    发明授权
    Local stall control method and structure in a microprocessor 有权
    微处理器中的局部失速控制方法和结构

    公开(公告)号:US06279100B1

    公开(公告)日:2001-08-21

    申请号:US09204535

    申请日:1998-12-03

    IPC分类号: G06F938

    摘要: A processor implements a local stall functionality in which small, independent circuit units are stalled locally with the condition causing a stall being first detected locally, then propagated to other small independent circuit units. Stall conditions for a functional unit are detected locally with reduced logic circuitry and also without waiting to receive condition information from other functional units that is transmitted over long wires. Local stall logic circuits are distributed over diverse areas of an integrated circuit so that stall conditions are detected locally. A local stall is expanded into a global stall by propagation to logic circuits beyond a local region in subsequent cycles. Local detection of stall conditions and local stalling eliminates many critical paths in the processor.

    摘要翻译: 处理器实现局部失速功能,其中小的独立电路单元在本地停止,导致局部首先检测到失速的状态,然后传播到其他小的独立电路单元。 通过减少的逻辑电路本地检测功能单元的失速条件,并且也不等待从通过长导线传输的其他功能单元接收条件信息。 局部失速逻辑电路分布在集成电路的不同区域,使得局部检测失速状态。 通过在随后的周期内传播到局部区域以外的逻辑电路,将局部扩展扩展为全局失速。 局部检测失速条件和局部停止消除了处理器中的许多关键路径。

    Maintaining data unit order in a network switching device
    9.
    发明授权
    Maintaining data unit order in a network switching device 有权
    维护网络交换设备中的数据单元顺序

    公开(公告)号:US08498306B2

    公开(公告)日:2013-07-30

    申请号:US13045312

    申请日:2011-03-10

    IPC分类号: H04L12/56

    摘要: Data units received by a network device may be classified into traffic flow classes in which the determined traffic flow class for a data unit may be dynamically refined as the data unit is processed by the network device. A dispatch component of the network device may receive data units associated with traffic flow classes. Parallel processing engines of the network device may receive the data units from the dispatch component and may generate, for a least one of the data units, a plurality of dynamically refined indications of the traffic flow class to which the data unit belongs. Additionally, an ordering component of the network device may include a plurality of re-order queues, where the at least one data unit successively progresses through at least two of the re-order queues in an order defined by the plurality of dynamically refined indications of the traffic flow class.

    摘要翻译: 由网络设备接收的数据单元可以被分类为业务流类别,其中所确定的数据单元的业务流类别可以由网络设备处理数据单元时动态地改进。 网络设备的调度组件可以接收与业务流类别相关联的数据单元。 网络设备的并行处理引擎可以从调度组件接收数据单元,并且可以为数据单元中的至少一个数据单元生成数据单元所属的业务流类别的多个动态精确的指示。 另外,网络设备的排序组件可以包括多个重新排序队列,其中至少一个数据单元以由多个动态精简指示定义的顺序连续地进行至少两个重排队列 交通流量类。

    Hardware support for instruction set emulation
    10.
    发明授权
    Hardware support for instruction set emulation 有权
    硬件支持指令集仿真

    公开(公告)号:US08069023B1

    公开(公告)日:2011-11-29

    申请号:US12202742

    申请日:2008-09-02

    IPC分类号: G06F17/50

    摘要: A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to extract read and write addressing from the nexthop instruction instead of performing this operation in microcode. A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to compare a nexthop read address to a special value and to indicate whether the nexthop read address matches the special value, instead of performing this operation in microcode. A method for determining a network address by performing a single extraction of bit fields of a tree instruction to allow multiple tree search processes to be performed.

    摘要翻译: 一种在专用硬件协助下仿真微代码中的下一跳指令的方法,用于从下一跳指令中提取读取和写入寻址,而不是在微码中执行该操作。 一种在专用硬件的协助下仿真微代码中的下一跳指令的方法,用于将下一跳读取地址与特殊值进行比较,并指示下一跳读取地址是否匹配特殊值,而不是以微码执行该操作。 一种通过执行树指令的位字段的单次提取来确定网络地址以允许执行多个树搜索处理的方法。