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11 条记录 (耗时 0.019 秒)

    Memory-logic semiconductor device
    1.
    发明授权
    Memory-logic semiconductor device 失效
    存储器逻辑半导体器件

    公开(公告)号：US06529397B2

    公开(公告)日：2003-03-04

    申请号：US09750068

    申请日：2000-12-29

    申请人： Shigetoshi Takeda ,  Taiji Ema ,  Peter Bruce Gillingham

    发明人： Shigetoshi Takeda ,  Taiji Ema ,  Peter Bruce Gillingham

    IPC分类号： G11C700

    CPC分类号： G11C15/043 ,  G11C15/04

    摘要： The semiconductor device has a plurality of basic units, each including a memory element and a logic element and having the same or bilateral symmetry structure. Each basic unit has a DRAM cell formed in a first active region, serially connected transistors of a logic element having second and third gate electrodes, first and second signal lines connected to the source/drain regions of the transistor pair, a third signal line connected to the second gate electrode, and a conductive connection terminal formed under the storage electrode of a DRAM capacitor and the third gate electrode. A semiconductor device having a plurality of basic units each including a memory cell and a logic cell formed on the same semiconductor substrate, the device being easy to manufacture and capable of high integration is provided.

    摘要翻译： 半导体器件具有多个基本单元，每个基本单元包括存储元件和逻辑元件，并具有相同或双边的对称结构。 每个基本单元具有形成在第一有源区中的DRAM单元，具有连接到晶体管对的源/漏区的第一和第二信号线的串联连接的具有第二和第三栅电极的逻辑元件的晶体管，第三信号线连接 以及形成在DRAM电容器的存储电极和第三栅电极下方的导电连接端子。 一种具有多个基本单元的半导体器件，每个基本单元各自包括形成在同一半导体衬底上的存储单元和逻辑单元，该器件易于制造并且能够高度集成。

    MOS image sensor
    3.
    发明授权
    MOS image sensor 有权
    MOS图像传感器

    公开(公告)号：US07592655B2

    公开(公告)日：2009-09-22

    申请号：US11216111

    申请日：2005-09-01

    申请人： Narumi Ohkawa ,  Shigetoshi Takeda ,  Yukihiro Ishihara ,  Kazuki Hayashi ,  Nobuhisa Naori ,  Masahiro Chijiiwa

    发明人： Narumi Ohkawa ,  Shigetoshi Takeda ,  Yukihiro Ishihara ,  Kazuki Hayashi ,  Nobuhisa Naori ,  Masahiro Chijiiwa

    IPC分类号： H01L31/062

    CPC分类号： H01L27/14603 ,  H01L21/76802 ,  H01L21/76897 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor image sensor includes: a semiconductor substrate having a number of pixels disposed in a matrix shape, the semiconductor substrate comprising a first region including a charge accumulation region of a photodiode and a floating diffusion and a second region including transistors, each having a gate electrode and source/drain regions; a first silicon oxide film formed above the semiconductor substrate, covering the surface of the charge accumulation region in the first region and formed as side wall spacers on side of the gate electrode walls of at lease some transistors in the second region; and a silicon nitride film formed above the first silicon oxide film, covering the source/drain regions in the second region and having an opening at least in an area above the charge accumulation region in the first region. The semiconductor image sensor is provided which has a high sensitivity and can supply an output with small noises.

    摘要翻译： 半导体图像传感器包括：具有以矩阵形状排列的多个像素的半导体衬底，所述半导体衬底包括包括光电二极管的电荷聚集区域和浮动扩散部的第一区域和包括晶体管的第二区域，每个具有栅极 电极和源极/漏极区域; 形成在所述半导体衬底上方的第一氧化硅膜，覆盖所述第一区域中的所述电荷累积区域的表面，并且在所述第二区域中的至少一些晶体管的所述栅极电极壁的侧面上形成为侧壁间隔物; 以及形成在所述第一氧化硅膜上方的氮化硅膜，覆盖所述第二区域中的所述源极/漏极区域，并且至少在所述第一区域中的所述电荷累积区域之上的区域中具有开口。 提供具有高灵敏度的半导体图像传感器，并且可以提供具有小噪声的输出。

    Solid-state image sensor
    5.
    发明授权
    Solid-state image sensor 有权
    固态图像传感器

    公开(公告)号：US07005690B2

    公开(公告)日：2006-02-28

    申请号：US11003380

    申请日：2004-12-06

    申请人： Masahiro Chijiiwa ,  Shigetoshi Takeda ,  Masaya Katayama

    发明人： Masahiro Chijiiwa ,  Shigetoshi Takeda ,  Masaya Katayama

    IPC分类号： H01L31/062 ,  H01L31/113

    CPC分类号： H01L27/14609 ,  H01L27/1463

    摘要： The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.

    摘要翻译： 固态图像传感器包括像素部分10，模拟电路部分12，数字电路部分14和输入/输出电路部分16。 数字电路部分14包括形成在围绕其第一区域的第一导电类型的半导体衬底20的第二区域中的第二导电类型的第一阱42c; 掩埋在第一区域中的第二导电类型的第一掩埋扩散层40c：在第一区域中形成在半导体衬底20的表面附近形成的第一导电类型的第二阱44b; 以及形成在第二阱44b上的第一晶体管38e。

    SOLID-STATE IMAGE SENSOR
    6.
    发明申请
    SOLID-STATE IMAGE SENSOR 有权
    固态图像传感器

    公开(公告)号：US20060011956A1

    公开(公告)日：2006-01-19

    申请号：US11003380

    申请日：2004-12-06

    申请人： Masahiro Chijiiwa ,  Shigetoshi Takeda ,  Masaya Katayama

    发明人： Masahiro Chijiiwa ,  Shigetoshi Takeda ,  Masaya Katayama

    IPC分类号： H01L31/113

    CPC分类号： H01L27/14609 ,  H01L27/1463

    摘要： The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.

    摘要翻译： 固态图像传感器包括像素部分10，模拟电路部分12，数字电路部分14和输入/输出电路部分16.数字电路部分14包括形成在第二导电类型的第二导体类型的第一阱42c 围绕其第一区域的第一导电类型的半导体衬底20的第二区域; 掩埋在第一区域中的第二导电类型的第一掩埋扩散层40c：在第一区域中形成在半导体衬底20的表面附近形成的第一导电类型的第二阱44b; 以及形成在第二阱44b上的第一晶体管38e。

    Semiconductor device with memory and logic cells
    8.
    发明授权
    Semiconductor device with memory and logic cells 失效
    具有存储器和逻辑单元的半导体器件

    公开(公告)号：US06465829B2

    公开(公告)日：2002-10-15

    申请号：US09749463

    申请日：2000-12-28

    申请人： Shigetoshi Takeda ,  Taiji Ema

    发明人： Shigetoshi Takeda ,  Taiji Ema

    IPC分类号： H01L27108

    CPC分类号： G11C15/04 ,  G11C15/043

    摘要： A semiconductor device has a plurality of basic units formed on a semiconductor substrate, each including a memory element and a logic element and having the same or bilateral symmetry structure. Each basic unit has a DRAM cell formed in a first active region, serially connected transistors of a logic element formed in a second active region and having second and third gate electrodes and source/drain regions with silicide layers, first and second signal lines connected to the source/drain regions of the transistor pair, a third signal line connected to the second gate electrode, and a conductive connection terminal formed under the storage electrode of a DRAM capacitor for connecting the storage electrode and third gate electrode. A semiconductor device is provided which has a plurality of basic units each including a memory cell and a logic cell formed on the same semiconductor substrate, the device being easy to manufacture and capable of high integration.

    摘要翻译： 半导体器件具有形成在半导体衬底上的多个基本单元，每个基本单元包括存储元件和逻辑元件，并具有相同或双边对称结构。 每个基本单元具有形成在第一有源区域中的DRAM单元，串联连接在第二有源区中的逻辑元件的晶体管，并且具有第二和第三栅极电极以及具有硅化物层的源/漏区域，第一和第二信号线连接到 晶体管对的源极/漏极区域，连接到第二栅极电极的第三信号线以及形成在用于连接存储电极和第三栅电极的DRAM电容器的存储电极下方的导电连接端子。 提供一种半导体器件，其具有多个基本单元，每个基本单元包括形成在同一半导体衬底上的存储单元和逻辑单元，该器件易于制造并且能够高度集成。

    Semiconductor device and method of manufacturing semiconductor device
    9.
    发明授权
    Semiconductor device and method of manufacturing semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US09024410B2

    公开(公告)日：2015-05-05

    申请号：US13606710

    申请日：2012-09-07

    申请人： Shigetoshi Takeda

    发明人： Shigetoshi Takeda

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.

    摘要翻译： 半导体器件包括形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的熔丝，形成在第一绝缘膜上方的第二绝缘膜和熔丝，并且包括到达保险丝的开口，以及形成第三绝缘膜 在第二绝缘膜之上和开口中。