公开(公告)号：US5710550A

公开(公告)日：1998-01-20

申请号：US516322

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

IPC分类号： G06F15/173 ,  H04Q11/04 ,  H03K17/0412

CPC分类号： G06F15/17375 ,  H04Q11/0478

摘要： A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data. The FPID further includes a memory controller for receiving each command from the host controller and for writing data included in the command into each memory cell of a particular subset of the first and second memory cells upon receipt of the command. The address included in the command indicates the particular subset into which the controller is to write the data. The number of memory cells included in the particular subset is a variable function of the address.

摘要翻译： 现场可编程互连设备（FPID）响应于来自主机控制器的命令，有选择地在信号端口之间路由信号。 每个命令包括地址和数据。 FPID包括开关单元阵列，每个开关单元互连一个单独的端口对，并且每个具有第一和第二控制信号输入。 当第一和第二控制信号均被断言时，开关单元在其互连的一对端口之间提供信号路径。 FPID包括用于存储数据的第一和第二组存储器单元。 每个第一存储器单元对应于开关单元中的单独单元，并根据其存储的数据选择性地断言或解除输入到相应开关单元的第一控制信号。 每个第二存储器单元对应于单独的开关单元组，并根据其存储的数据选择性地断言或解除输入到相应组的每个开关单元的第二控制信号。 FPID还包括存储器控制器，用于从主机控制器接收每个命令，并且用于在接收到命令时将包括在命令中的数据写入第一和第二存储器单元的特定子集的每个存储单元。 命令中包含的地址表示控制器写入数据的特定子集。 包含在特定子集中的存储单元的数量是地址的可变函数。

公开(公告)号：US5790048A

公开(公告)日：1998-08-04

申请号：US961545

申请日：1997-10-30

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： H03K19/173 ,  H04Q1/00 ,  G06F13/00

CPC分类号： H03K19/1736

摘要： A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

摘要翻译： 交叉点交换机通过从主机控制器的路由数据定义的路由模式在其终端之间路由信号。 交叉点开关包括传输晶体管阵列。 每个通过晶体管在导通时提供一个信号路径，互连独立的一对开关端子。 交叉点开关还包括两个静态随机存取存储体。 每个存储体存储定义单独路由模式的路由数据，并产生反映其存储的数据的单独的一组输出信号。 多路复用器将所选择的一个存储器组的输出信号传送到开关阵列，以控制其传输晶体管，使得开关阵列实现由所选存储体中的数据定义的布线图案。 通过将定义不同路由模式的路由数据加载到两个存储体中，主控制器随后可以通过切换多路复用器的控制输入来快速地使交叉点开关交替在两个路由模式之间。

公开(公告)号：USD694300S1

公开(公告)日：2013-11-26

申请号：US29422711

申请日：2012-05-23

申请人： Sandip Shrikant Sathe

设计人： Sandip Shrikant Sathe

公开(公告)号：US5734334A

公开(公告)日：1998-03-31

申请号：US516320

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： H03K19/173 ,  H04Q1/00

CPC分类号： H03K19/1736

摘要： An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.

摘要翻译： 电子交叉开关采用开关阵列，用于在其端子之间选择性地路由数字和模拟信号。 每个端子的独立端口为数字和模拟信号流入和流出交换机提供了路径。 每个端口可被配置为在三态控制信号的控制下具有或不具有三态缓冲器，以响应于时钟和时钟使能信号来选择性地锁存输入或输出信号，以及缓冲通过或者流过开关端子的信号， 没有输入方向控制信号。 为所有端口提供一组控制输入，允许外部主机与每个端口并行发送控制信号。 每个端口可以被编程为选择其任何控制输入作为其三态，时钟使能，时钟或方向控制信号。

公开(公告)号：US5717871A

公开(公告)日：1998-02-10

申请号：US516319

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： G06F13/40 ,  H04L12/56 ,  H04Q3/68 ,  G06F3/00

CPC分类号： G06F13/4022 ,  H04L49/25 ,  H04Q3/68 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13106 ,  H04Q2213/13141 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller. Each port stores an internal port address and when the key address matches the port address, the port asserts an internal "KEY" signal. Each port may be configured to use the KEY signal selectively as either its tristate, clock enable, clock or direction control signal.

摘要翻译： 电子交叉开关采用开关阵列，用于在其端子之间选择性地路由信号。 为每个端子提供的单独端口缓冲流入和流出开关的信号。 每个端口可以被配置为在三态控制信号的控制下操作有或没有三态缓冲，以响应于时钟和时钟使能信号来选择性地锁存输入或输出信号，以及响应于缓冲转换到终端的信号 到方向控制信号。 为所有端口提供一组控制输入，允许外部主机与每个端口并行发送控制信号。 每个端口可以被编程为选择其任何控制输入作为其三态，时钟使能，时钟或方向控制信号。 还向所有端口提供并行“键”总线，用于从主机控制器传送密钥地址。 每个端口存储内部端口地址，当密钥地址与端口地址匹配时，端口置位一个内部“KEY”信号。 每个端口可以被配置为选择性地使用KEY信号作为其三态，时钟使能，时钟或方向控制信号。